New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency. Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.” Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.
SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA CHI Issue B, and verification automation solutions including Auto SoC Testbench Generation and AutoPerformance for AMBA protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of source code test suites and VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications.
Safety features have always been important in the automotive industry; it has certainly become the most critical requirement for autonomous vehicles. Have you ever wondered what technology makes it possible for multiple sensors located at front, rear sections and inside the doors to work in a coordinated manner for early crash detection and operate the vehicles air bags thereby protecting precious human life?
PCIe is a multi-layered serial bus protocol which implements dual-simplex link. It provides high speed data transfer and low latency owing to its dedicated point to point topology. To accelerate verification and device development time for PCIe based sub-systems, PIPE (PHY Interface for the PCI Express) architecture was defined by Intel. PIPE is a standard interface defined between PHY sub-layer (PCS – Physical Coding sub-layer) and MAC (Media Access Layer).
In this era of revolutionary technologies, memory plays a vital role in any application that requires high-speed processing. High-resolution graphics require high-speed and high-bandwidth graphics memory, resulting in rapid adoption of next generation memory technology High-Bandwidth Memory (HBM). HBM is finding its way into leading-edge graphics, networking, HPC (High Performance Computing), and Artificial Intelligence systems; for example, decoders for a video signal, fully autonomous vehicles, neural network designs, and other advanced applications that demand low power and massive bandwidth. Our previous memory blog – Next generation memory technologies: Ready to take the verification challenges?, discussed several next generation memory technologies across applications. This blog will review the details of HBM, a next generation memory technology for graphics, networking and HPC.
Is your latest NVMe design taking advantage of Streams? Adoption of this new NVMe technology is gaining momentum with Synopsys customers. Streams are part of the new, optional, Directives feature introduced in the NVMe 1.3 specification. Directives allow the passing of metadata between hosts and controllers via existing NVMe commands. Streams are unique in that they are the only I/O based Directive available in the 1.3 specification.
Ever since Arm released the Arm® AMBA® 5 AHB5 protocol specifications, questions have arisen among users in the design and verification community—”Why AHB5?”, “What is new in AHB5?” etc. This post initiates a short series of blogs in which we will address these questions and introduce the new features of AMBA 5 AHB5.
In June 2017, PCI-SIG announced the new PCI Express 5.0 specification, at the PCI-SIG DevCon. The new version of the specification doubled bit rate to 32GT/s per lane providing about 128GB/s bandwidth for a x16 Link (16 lanes). The chart below provides a comparison of bit-rate and bandwidth for the different PCIe Generations.
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.