VIP Central

With the arrival of HDMI 2.1 comes an array of remarkable features including the capability to support up to 10K resolutions at 120Hz. Such high resolutions are supported for a wider range of display applications such as externally connected displays (i.e. PC monitors and televisions), embedded display interfaces within mobile systems, and automotive infotainment systems. But with higher resolutions comes the requirement for higher bandwidth.

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With the rise of cloud computing and large scale data centers, both developers and consumers are demanding for more efficient ways to rapidly access their data. Seeing the advantage of its high performance, the storage industry is quickly adopting the Non-Volatile Memory Express (NVMe) standard. The NVMe™ standard continues to push the storage envelope with version 1.3 and beyond in all types of computing environments from mobile to data center. One of the key features of the NVMe™ standard is its ability to handle virtualization.

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Higher performance at lower power is the most critical requirement of SoC designs, specifically those targeted towards mobile and consumer electronics applications. VESA (Video Electronics Standards Association), the technical standards organization for computer display standards, came up with a new power saving feature called PSR (Panel Self Refresh) in eDP 1.3. It is also available as an optional feature in DisplayPort. PSR helps to extend battery life in mobile phones, notebooks, and tablets, and is quickly being adopted in high-end designs.

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In today’s world of smartphones and tablets, high speed data at low power consumption is becoming increasingly important. MIPI M-PHY supports multiple applications with high data bandwidth and low power consumption which makes it a popular specification for mobile devices. Applications like JEDEC UFS 3.0 and MIPI UniPro 1.8 now support MIPI M-PHY 4.1 which provides high speed data at a rate of nearly 11Gbps (HS_G4). To learn more about latest UFS and UniPro specifications read our previous blog “High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0”. Data at such a high speed can lead to inter-symbol-interference (ISI). M-PHY provides a safety measure to prevent the loss of data at HS_G4. In this blog, we are going to talk about the ‘ADAPT’ feature and its advantages which were introduced in M-PHY 4.0.

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HDMI (High-Definition Multimedia Interface) is a proprietary audio/video interface for transferring uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controller, to a compatible computer monitor, video projector, digital television, or digital audio device. HDMI is a digital replacement for analog video standards, represented using one of several luminance/color-difference color spaces. We introduced HDMI 2.1 in our previous blog – HDMI 2.1: Channeling the GenX Audio Video Experience. In this blog we will discuss about evolution and key features of HDMI from v1.4 to v2.1.

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Flash storage is one of the most important component of a smart phone, and with every new version comes higher memory capacity and performance. The most rapidly adopted flash memory technology in recent years is Universal Flash Storage (UFS), with UFS v2.1 providing a maximum data rate of ~11Gbps. JEDEC has come up with the faster next-generation UFS v3.0 which uses MIPI UniPro v1.8 (Unified Protocol) and MIPI M-PHY v4.1 as interconnect layer.

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In mid-2014, the USB Type-C standard was announced, which provided a thinner, reversible connector and ever evolving ecosystem of new platforms like MHL, DisplayPort, HDMI, and Thunderbolt over Type-C. USB Type-C is quickly being integrated into most high end and newly-released mid-range smart phones offering the reversible Type-C connector. It is also becoming the connector of choice for IoT, display, gaming, and other emerging applications. Synopsys’ Subsystem Verification Solution for USB Type-C™ is rapidly being adopted by customers. Read more about the adoption of Synopsys’ USB Type-C Subsystem Verification Solution by ASIX.

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One could argue that camera has been the most fascinating feature of smart phones in recent years. The latest camera phones are capable of not only capturing minute details with multi-mega pixels, but also sensing the presence of various objects. MIPI CSI-2 (Camera Serial Interface) is a high-bandwidth interface between a camera and a host processor. MIPI CSI-2 v1.1 got introduced in 2011 to fulfill the basic camera requirements of mobile applications. Next generation MIPI CSI-2 v2.0 and v2.1 have evolved to meet the requirements of emerging imaging and vision applications like wearables, IoT, drones, automotive, and security surveillance beyond smart phones. Read our previous blog to know more about MIPI CSI-2 v2.0: Emerging Applications in IoT, Drones and Automotive. The new features of MIPI CSI-2 v2.1 are outlined below:

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New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency.  Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.”  Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.

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SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?

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