Higher storage performance at a lower cost can create a bottleneck in the design of storage devices. In order to achieve higher performance, devices must use on chip DRAM, which adds to the overall cost. This is where Unified Memory Extension (UME), a JEDEC specification, comes into the picture. It is defined as extension to the JEDEC UFS (Universal Flash Storage) specification. JEDEC UFS device uses NAND flash technology for data storage. Unified Memory (UM) allows users to use part of the host memory as the device’s internal memory. Since the host memory is already available in large capacities, this mechanism provides a much bigger space for the device to use as a Write Buffer (WB) cache or to store information such as Logical to Physical (L2P) address translation tables. The UM area is physically located on the host side but ultimately belongs to the device, thereby replacing the device-integrated RAM, and reducing overall cost. Large space availability means the device can store larger amounts of WB of L2P table information resulting in higher storage performance.
First USB 3.2 VIP and TestSuite: Enhances the Verification Solution for USB IP, SoC and Type-C Subsystems
USB has literally become universal and present in every device ranging from smart phones and personal computers, IoT and wearables, storage and networking, consumer electronics and gaming consoles, automotive and many other emerging verticals. The success of USB can be attributed to innovation with each new generation—the capability to transfer data as well as supply power for charging devices and ease-of-use with a variety of connectors and form factors.
HDMI (High Definition Multimedia Interface), an audio video interface, has been around for quite some time connecting our TVs, computers, video game consoles, Blu-ray players, cable boxes, etc., to deliver top-quality audio video experience.
The ordering of memory transactions in Arm® AMBA® protocol is a significant requirement, i.e. the sequence of memory updates/accesses must follow a defined ordering as per the specification. Ordering is important for synchronization events by a processor with respect to retiring load/store instructions. AMBA ACE barrier transactions are used for maintaining the memory ordering across a system. The learning curve to understand barrier transactions may become a barrier to verify your design thoroughly. This blog provides insight, making it easier to understand and verify the barrier transactions. The blog will cover different types of barrier transactions, usage, and domain boundaries.
Sensors are everywhere surrounding us at home, office, cars, industry and everything else we are using today. It all started with the thermostat and first motion sensor used for an alarm system invented somewhere in 1950s. Over the period of time, rapid increase of sensors used across various applications created significant challenges, there was a need of sophistication in terms of size, electronics, packaging and integration of practically every kind of sensor one can think of. A modern sensor works the same way similar to the sensor decades ago, but is now smaller, better and much more reliable.
In our previous blog on SAS, we discussed about SAS 24G new encoding and features. In the series of SAS blogs, here we shed some light on other generations of SAS that are still hot in the market.
The two fundamental requirements of every mobile device is speed and power, with the biggest challenge being that both are inversely proportional to each other. One simply cannot have both, because with higher speed comes higher power consumption. With the ever increasing demand for higher resolution graphics and media to enrich the user experience, there has been a significant addition to data processing that requires high speed data transfers. Even though the devices are capable of capturing and playing back high quality media, the storage unit is not fast enough to match the required transfer speeds. This is an out of sync combination and one of the biggest challenges for mobile designs. The problem here is that, a memory system is required to be capable enough to perform read write operations at high speed without adding any significant numbers to power consumption.
The DDR PHY Interface (DFI) is used in several consumer electronics devices including smart phones. DFI is an interface protocol that defines signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices, and between MC (Micro Controller) and PHY. DFI is applicable to all DRAM protocols including DDR4, DDR3, DDR2, DDR, LPDDR4, LPDDR3, LPDDR2 and LPDDR.
AMBA AXI exclusive access may look simple at first glance, but as we delve deeper into it, we find the different flavors of exclusive access. The possibility of these different scenarios and combinations poses a tough challenge in verifying the critical feature in AMBA-based designs. This blog primarily focusses on exclusive access in AMBA AXI3, the concept, its different flavors and how Synopsys VIP can be leveraged to overcome the corresponding verification challenges.