VIP Central

Archive for the 'Uncategorized' Category

 

An Introduction to the CXL Device Types

Compute Express Link (CXL) is the latest specification in interconnect technology for high bandwidth devices. It provides high-speed, efficient connectivity from CPUs to other components of the high-performance computing platform.

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Posted in Interface Subsystems, Uncategorized, UVM |

 

Simplify Entertainment with HDMI 2.1 eARC

HDMI (High-Definition Multimedia Interface) has been a part of our entertainment systems for nearly two decades now. Though the look of the cable has remained the same over the years, the input has undergone many improvements since its release in 2002.

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Posted in Debug, Display, DisplayPort, Uncategorized, UVM |

 

Deciphering the New TileLink Standard

Increasing complexities of processor architectures with limited overall performance scale-up have created a demand for a domain specific architecture to ensure extensive performance scaling. – this is when RISC-V began to gain momentum. RISC-V is gathering widespread attention throughout sectors like datacenter accelerators, mobile & wireless, IoT, etc. for its extensibility. Many industry leaders are beginning to adopt RISC-V for its open source availability that reduces time-to-market and cost effectiveness while at the same time scaling up the overall performance and leaving room for innovation and automation.

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Posted in Mobile SoC, Processor Subsystems, Uncategorized |

 

The Power Of HDMI ARC

HDMI ARC, What is it and Why You Should Care?

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Posted in Display, HDMI, Uncategorized |

 

Run Faster, Welcome 800G and Terabit Speeds with Ethernet 802.3ck

IP traffic has been growing at a rate many could not have imagined. Driven by expanding Internet users and devices that yield faster wireless and fixed broadband access, the expeditious ethernet data rate has now reached to 400G. From 1Gbps in 1997, to 10Gbps in 2004, 100 Gbps in 2010, it took a while for the next set up to 400 Gbps.

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Posted in Ethernet, FlexE, Uncategorized |

 

Demystifying PCIe PIPE 5.1 SerDes Architecture

Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.

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Posted in PCIe, Uncategorized |

 

Arm TechCon 2019 – Recap

Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.

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Posted in AMBA, Interconnects, Mobile SoC, Processor Subsystems, Uncategorized |

 

Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings

We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.

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Posted in LPDDR, Memory, Uncategorized |

 

HBM Performance Verification Made Easy

HBM2E (High Bandwidth Memory) is a high-performance 3D-stacked DRAM used in high-performance computing and graphic accelerators. It uses less power but posts higher bandwidth than graphics cards relying on DDR4 or GDDR5 memory. Validating the performance and utilization of memory is a big challenge for users due to complex structure of SoC and the subsystem attached to it such as memory subsystem, interconnect bus, and processor.

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Posted in Debug, Uncategorized |

 

Detect & Avoid Memory Bottlenecks with Memory VIP

The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. For example, have you spent sleepless nights looking for ways to identify the performance bottlenecks and root cause them in your Memory Controller/PHY and Subsystem verification project?

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Posted in Uncategorized |