VIP Central

Archive for the 'Uncategorized' Category

 

How to Reduce Memory Model Debug Time

Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?

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Posted in Debug, Memory, Uncategorized |

 

Ethernet Time-Sensitive Network (TSN): A Boon for Automotive Audio-Video Bridging (AVB) Applications

Autonomous cars, vehicle communication and infotainment electronic systems are prevalent in today’s automobiles and everyday life. But, what does this mean for SoCs today?

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Posted in Automotive, Data Center, Ethernet, Uncategorized |

 

LPDDR5: Meeting Power, Performance, Bandwidth, and Reliability Requirements of AI, IoT and Automotive

The semiconductor industry is buzzing with new technologies – Artificial Intelligence (AI), Machine Learning (ML), IoT, Automotive, etc. – bringing a revolution by easing out our day-to-day lives and improving considerably performance, bandwidth and reliable data processing and transfer. Reliability and data integrity are even more important for safety critical verticals where even the slightest error can be catastrophic. Stepping up to meet industry trends, JEDEC recently announced its fifth revision of LPDDR standard JESD209-5 which is all equipped to match the latest bandwidth, power, performance, and reliability trends. Immediately following this, Synopsys announced the Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5. Strengthening our leadership in memory VIP, recently we also announced the Industry’s First DDR5 NVDIMM-P Verification IP, showing our continued collaboration with leading memory vendors.

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Posted in AI, Automotive, IoT, LPDDR, Memory, Uncategorized |

 

Signing off PCIe 5.0 Verification with Synopsys VIP

PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations.  Aligned with this, Synopsys also announced the collaboration of  its Design and Verification Solutions with  Astera Labs to Develop Industry’s First PCIe 5.0 Retimer SoC. Emerging applications like AI, cloud, data center, and 5G have been driving the exponential increase in bandwidth requirements and PCIe has evolved to meet these increasing requirements.

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Posted in CCIX, Data Center, PCIe, Uncategorized |

 

How 8k UHD Displays for Emerging Technologies are Enabled in MIPI DSI

High resolution 8k UHD displays for emerging technologies like connected cars, IoT, and AR/VR (Augmented/Virtual Reality) require high bandwidth to support the high-resolution transmission. MIPI DSI is the widely used display interface, but the bandwidth provided by PHY layers isn’t sufficient enough to support the high-resolution displays; therefore, a compression technique like DSC (Display Stream Compression) is required. One of our recent blog discussed about DSC 1.2 in HDMI 2.1 – High Resolution Displays for Mobile, TV, PC and Automotive Enabled by DSC 1.2 in HDMI 2.1. In this blog, we will see how DSC 1.2 enables MIPI DSI to support the high-resolution displays for emerging applications.

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Posted in Automotive, Display, DSC, DSI, Uncategorized |

 

Trending Articles on DDR5/LPDDR5, DFI 5.0, PCIe 5.0, UFS 3.0, and Type-C

We recently published the VIP Newsletter for Jan 2019. It provides the latest information on Verification IP, including blogs, trending topics, industry-leading announcements, in-depth technical articles, videos and webinars. The Q1 2019 edition of the newsletter is now available, covering content on new VIP for next-generation protocol specifications as well as updates on existing VIP. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in Uncategorized |

 

Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols  and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized |

 

A Joint Webinar by Synopsys and NVM Express™ Organization – Virtualization and NVMe

With the rise of cloud computing and large scale data centers, both developers and consumers are demanding for more efficient ways to rapidly access their data. Seeing the advantage of its high performance, the storage industry is quickly adopting the Non-Volatile Memory Express (NVMe) standard. The NVMe™ standard continues to push the storage envelope with version 1.3 and beyond in all types of computing environments from mobile to data center. One of the key features of the NVMe™ standard is its ability to handle virtualization.

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Posted in Data Center, events, NVMe, PCIe, Storage, Uncategorized |

 

Overcoming USB Type-C Verification Challenges

In mid-2014, the USB Type-C standard was announced, which provided a thinner, reversible connector and ever evolving ecosystem of new platforms like MHL, DisplayPort, HDMI, and Thunderbolt over Type-C. USB Type-C is quickly being integrated into most high end and newly-released mid-range smart phones offering the reversible Type-C connector. It is also becoming the connector of choice for IoT, display, gaming, and other emerging applications. Synopsys’ Subsystem Verification Solution for USB Type-C™ is rapidly being adopted by customers. Read more about the adoption of Synopsys’ USB Type-C Subsystem Verification Solution by ASIX.

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Posted in Automotive, Mobile SoC, Type C, Uncategorized, USB |

 

Bye Bye Bottlenecks – Automated SoC Performance Verification is Here!

SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?

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Posted in Automotive, Data Center, DDR, DFI, events, HBM, LPDDR, Memory, Uncategorized |