Using Synopsys Smart Monitors to Improve System Performance of Your Arm SoCs
Highlights
Posted in AXI, Uncategorized, ZeBu EP1
Synopsys TileLink Interconnect Verification IP for RISC-V SoCs
What is RISC-V?
Posted in Interface Subsystems, Processor Subsystems, Uncategorized
Diving Into the Components of ML-Based Regression Failure Analysis and Debug
Recently we wrote about how AI-driven debug automation technology can accelerate the root-cause analysis of regression failures. In that blog we introduced the Synopsys Verdi Regression Debug Automation (RDA) technology that helped customers like MediaTek achieve a 4X improvement in identifying root-causes of failures in their design. This blog will take a deeper look into the components of this RDA technology, explain how they work and how users can take advantage to achieve similar results.
Posted in Debug, Uncategorized, Verdi
Say Goodbye to blank screens with HDMI’s Quick Media Switching
Posted in AI, Data Center, Display, HDMI, Uncategorized
Coverage Models – Filling in the Holes for Memory VIP
Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
Posted in Uncategorized
HBM3: Next generation memory standard for solving high density and complex computational problems
In this era of technology revolution, there is a continuous progression in domains like AI applications, high end servers, and graphics. These applications require fast processing and high densities for storing the data, where High Bandwidth Memory (HBM) provides the most viable memory technology solution. Our previous memory blog HBM2 memory for graphics, networking and HPC explored this protocol with data transfer rate of 2GT/s with stacked architecture of 8-Hi stacks (8 die).The HBM2-extension (HBM2E) architecture provided further improvement on top of HBM2 with 3.2 GT/s transfer rate and 12-Hi stack architecture with individual die density upto 8Gb and overall density of 24GB.
Posted in Data Center, Debug, DesignWare, HBM, Uncategorized
Synopsys Verification Continuum ® on AWS – Join Us at DVCon US 2021
Verifications account for almost 70% of the time and resources consumed during chip development. Moving some or even all of logic simulation to cloud allows customers to free up valuable on-premises resources for other workloads. The deployment of Synopsys’ functional verification solutions on the AWS cloud platform enables accelerated development and verification of breakthrough connectivity technology and SoCs. AWS cloud enables users to take advantage of elastic infrastructure resources to address the increasing capacity requirements for semiconductor simulations.
Synopsys at DVCon US 2021 – Join us!
Join us March 1- 4 at DVCon US 2021, to learn how we help customers optimize chips for power, performance, and cost and cut months off their project schedules.
Posted in Cloud, Data Center, DVCON
The Fascinating Path of CXL 2.0 Device Discovery
In the CXL ecosystem the host software uses enumeration as the first step to discover CXL devices connected in the system.
Posted in Uncategorized
8K Ultra HD: A Giant Leap for High Definition Televisions
Lately television lovers across the world have an even better reason to be glued to the small screens, as 8K Ultra HD TVs have made their way to the market. The HDMI forums most recently released specification, v2.1, explains “higher video resolutions support a range of high resolutions and faster refresh rates including 8K60Hz and 4K120Hz for immersive viewing and smooth fast-action detail…” Most of us are familiar with the word “resolution”, but do we really know this term well?
Posted in Camera, Display, HDMI, Uncategorized
