VIP Central

Archive for the 'Uncategorized' Category

 

Arm TechCon 2019 – Recap

Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.

Continue Reading...

Posted in AMBA, Interconnects, Mobile SoC, Processor Subsystems, Uncategorized |

 

Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings

We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.

Continue Reading...

Posted in LPDDR, Memory, Uncategorized |

 

HBM Performance Verification Made Easy

HBM2E (High Bandwidth Memory) is a high-performance 3D-stacked DRAM used in high-performance computing and graphic accelerators. It uses less power but posts higher bandwidth than graphics cards relying on DDR4 or GDDR5 memory. Validating the performance and utilization of memory is a big challenge for users due to complex structure of SoC and the subsystem attached to it such as memory subsystem, interconnect bus, and processor.

Continue Reading...

Posted in Debug, Uncategorized |

 

Detect & Avoid Memory Bottlenecks with Memory VIP

The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. For example, have you spent sleepless nights looking for ways to identify the performance bottlenecks and root cause them in your Memory Controller/PHY and Subsystem verification project?

Continue Reading...

Posted in Uncategorized |

 

How to Reduce Memory Model Debug Time

Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?

Continue Reading...

Posted in Debug, Memory, Uncategorized |

 

Ethernet Time-Sensitive Network (TSN): A Boon for Automotive Audio-Video Bridging (AVB) Applications

Autonomous cars, vehicle communication and infotainment electronic systems are prevalent in today’s automobiles and everyday life. But, what does this mean for SoCs today?

Continue Reading...

Posted in Automotive, Data Center, Ethernet, Uncategorized |

 

LPDDR5: Meeting Power, Performance, Bandwidth, and Reliability Requirements of AI, IoT and Automotive

The semiconductor industry is buzzing with new technologies – Artificial Intelligence (AI), Machine Learning (ML), IoT, Automotive, etc. – bringing a revolution by easing out our day-to-day lives and improving considerably performance, bandwidth and reliable data processing and transfer. Reliability and data integrity are even more important for safety critical verticals where even the slightest error can be catastrophic. Stepping up to meet industry trends, JEDEC recently announced its fifth revision of LPDDR standard JESD209-5 which is all equipped to match the latest bandwidth, power, performance, and reliability trends. Immediately following this, Synopsys announced the Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5. Strengthening our leadership in memory VIP, recently we also announced the Industry’s First DDR5 NVDIMM-P Verification IP, showing our continued collaboration with leading memory vendors.

Continue Reading...

Posted in AI, Automotive, IoT, LPDDR, Memory, Uncategorized |

 

Signing off PCIe 5.0 Verification with Synopsys VIP

PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations.  Aligned with this, Synopsys also announced the collaboration of  its Design and Verification Solutions with  Astera Labs to Develop Industry’s First PCIe 5.0 Retimer SoC. Emerging applications like AI, cloud, data center, and 5G have been driving the exponential increase in bandwidth requirements and PCIe has evolved to meet these increasing requirements.

Continue Reading...

Posted in CCIX, Data Center, PCIe, Uncategorized |

 

How 8k UHD Displays for Emerging Technologies are Enabled in MIPI DSI

High resolution 8k UHD displays for emerging technologies like connected cars, IoT, and AR/VR (Augmented/Virtual Reality) require high bandwidth to support the high-resolution transmission. MIPI DSI is the widely used display interface, but the bandwidth provided by PHY layers isn’t sufficient enough to support the high-resolution displays; therefore, a compression technique like DSC (Display Stream Compression) is required. One of our recent blog discussed about DSC 1.2 in HDMI 2.1 – High Resolution Displays for Mobile, TV, PC and Automotive Enabled by DSC 1.2 in HDMI 2.1. In this blog, we will see how DSC 1.2 enables MIPI DSI to support the high-resolution displays for emerging applications.

Continue Reading...

Posted in Automotive, Display, DSC, DSI, Uncategorized |

 

Trending Articles on DDR5/LPDDR5, DFI 5.0, PCIe 5.0, UFS 3.0, and Type-C

We recently published the VIP Newsletter for Jan 2019. It provides the latest information on Verification IP, including blogs, trending topics, industry-leading announcements, in-depth technical articles, videos and webinars. The Q1 2019 edition of the newsletter is now available, covering content on new VIP for next-generation protocol specifications as well as updates on existing VIP. In case you missed the latest buzz on Verification IP, you can read it here.

Continue Reading...

Posted in Uncategorized |