VIP Central

Archive for the 'Test Suites' Category

 

PCIe: Monitors and Test Suites

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP Monitor and Test Suites http://bit.ly/1DHIdyQ

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM |

 

Freescale and Xilinx Engineers: Managing SoC Verification Complexity

At DVCon 2015, a couple of our key customers shared their viewpoints on how they manage growing verification complexity. This video begins with Michael Sanie highlighting the Synopsys Verification Continuum, and several key technologies that currently address the industry’s need to “Shift-Left” for faster time-to-market. Later, Amol Bhinge of Freescale and Prashanth Gurunath of Xilinx share how their leading SoC design teams have achieved success by collaborating with Synopsys.

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Posted in AMBA, Audio, Camera, DDR, Debug, DesignWare, Display, HDMI, Interface Subsystems, LPDDR, Methodology, MIPI, Mobile SoC, PCIe, SystemVerilog, Test Suites, USB, UVM |

 

PCIe Verification IP Overview

In this video, VIP Senior Manager Paul Graykowski of Synopsys gives an overview of the PCI Express Verification IP: http://bit.ly/1DTe6si

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM |

 

SystemVerilog Protocol Compliance: Why Source-code Test Suites?

Here, Bernie DeLay explains the architecture and scope of the SystemVerilog source-code test suites included with the Synopsys VIP titles, and how they minimize the effort associated with protocol compliance testing. He uses a USB VIP in a DesignWare environment with AXI as an example  http://bit.ly/1BHUgQg

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Posted in AMBA, DesignWare, Methodology, SystemVerilog, Test Suites, USB, UVM |

 

SystemVerilog Test Suites Accelerate IP-to-SoC Reuse

Verifying complex SoCs takes a lot of effort. Our user surveys show that around 70% of the engineering resource involved in taping out a complex SoC is spent on verification, with half of that time consumed by debug.

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Posted in Methodology, PCIe, SystemVerilog, Test Suites |