VIP Central

Archive for the 'Test Suites' Category

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |

 

Synopsys Verification Continuum at DAC 2016

The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.

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Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM |

 

Integrate USB Test Suite Quickly to Jump Start Verification

SoC being designed today are getting complex day by day and verification complexity increases exponentially not only due to the complexity of design but also due to the complexity of protocols. Emerging new protocols make it further difficult due to steep learning curve. Writing test cases to cover the entire protocol becomes 3-4 man year job for complex protocols like USB, PCIe, and Ethernet etc. Synopsys provides System Verilog/UVM source code test suites to verify complex protocols. Source code is provided and tests can be extended, and customized easily. You can save the efforts and time by using Synopsys test suites to jump start verification and achieve accelerated coverage closure. In this blog, we will give an overview of the USB test suite focusing on ease of integration and use.

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Posted in Test Suites, USB |

 

Celebrating the Holiday Season with VIPs

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Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB |

 

First Ethernet 400G VIP to Enable Next-Gen Networking and Communications SoCs

On Monday, Synopsys announced the availability of the industry’s first verification IP (VIP) and source code test suite to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard (400GbE). To understand how it will enable next generation networking and communication systems, we take a look at the evolution of the Ethernet.

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Posted in Data Center, Ethernet, Methodology, SystemVerilog, Test Suites, UVM |

 

Synopsys AMBA 5 AHB5 Verification IP: What’s It All About?

This week, at ARM Techcon 2015, Synopsys announced the availability of our VC Verification IP for the new ARM AMBA 5 Advanced High-Performance Bus 5 (AHB5) interconnect. The AHB5 protocol is an update to the widely adopted AMBA 3 AHB3 specification. It extends the TrustZone security foundation from the processor to the entire system for embedded designs. AHB5 supports the newly announced ARMv8-M architecture which drives security into the hardware layer to ensure developers have a fast and efficient way of protecting any embedded or Internet of Things (IoT) device.

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Posted in AMBA, SystemVerilog, Test Suites |

 

PCIe Gen4 – VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites

Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging.  This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure.

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Posted in Debug, Methodology, PCIe, SystemVerilog, Test Suites, UVM |

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM |

 

Performance Advantages of Synopsys VIP

In this video, you will learn how several users are benefiting from the performance advantage of using Synopsys VIP  http://bit.ly/1Kau83g

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Posted in Debug, SystemVerilog, Test Suites, UVM |

 

PCIe: Monitors and Test Suites

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP Monitor and Test Suites http://bit.ly/1DHIdyQ

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM |