Verification Central

Archive for the 'SystemVerilog' Category


Get Ready for IoT with Synopsys PCIe VC Verification IP Workshop

Internet of Things (IoT) is connecting billions of intelligent “things” to our fingertips. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications. Servers powering the cloud will have to scale to handle these billions of intelligent things. As a preparation to that PCIe Gen 4 has been introduced. It is capable of supporting 16 T transfers/s. Current primary market driver for the PCIe Gen4 application seems to be server storage space.

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Posted in Debug, Methodology, MIPI, MPHY, PCIe, SystemVerilog


The Synopsys NVMe VIP: A High Level View

Overview NVM Express or the Non-Volatile Memory Host Controller Interface (its prior name was NVMHCI, now shortened to NVMe) is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. The current Synopsys NVMe Verification IP (VIP) is a comprehensive testing vehicle which consists of two main subsystems – the first is the SVC (System Verification Component), the second is SVT (System Verification Technology).  The SVC layers are associated with the actual NVMe (and PCIe, etc.) protocol layers.  The SVT provides a verification methodology interface to UVM and other methodologies such as VMM and OVM.

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Posted in MPHY, NVMe, PCIe, Storage, SystemVerilog


Introducing Synopsys VIP for PCIe Gen4

Here, Paul Graykowski, Corporate Applications Engineer at Synopsys, describes what our Verification IP for PCIe Gen4 can do for you.

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Posted in Data Center, Debug, Methodology, PCIe, SystemVerilog, UVM


SoC Leaders Verify with Synopsys: DAC 2015 Verification Luncheon

Featuring speakers from Altera, AMD, ARM, Cavium and Freescale During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.

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Posted in Debug, Methodology, Mobile SoC, Processor Subsystems, Success Stories, SystemVerilog, UVM


Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM


DAC 2015, San Francisco: Must-See Verification Sessions

It’s going to be an exciting week for  designers and verification engineers at the Design Automation Conference in San Francisco this week. Here’s a list of activities we recommend:

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Posted in Methodology, SystemVerilog, UVM


Performance Advantages of Synopsys VIP

In this video, you will learn how several users are benefiting from the performance advantage of using Synopsys VIP

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Posted in Debug, SystemVerilog, Test Suites, UVM


AMBA System Monitor, Scoreboarding and Beyond

In my previous blog post, How do you Verify the AMBA System Level Environment? we discussed how to enable SOC verification engineers to create highly configurable AMBA fabric.

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Posted in AMBA, Methodology, SystemVerilog, UVM


PCIe: Monitors and Test Suites

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP Monitor and Test Suites

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM


PCIe: Accelerating Debug

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the debug process:

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Posted in Debug, PCIe, SystemVerilog, UVM