From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage.
We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance analyzer and protocol debug. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in Automotive, Camera, CSI, Data Center, DDR, Debug, DFI, Display, DisplayPort, DSC, events, Flash, HDMI, LPDDR, Memory, MIPI, Mobile SoC, NVMe, PCIe, Storage, Test Suites, ToggleNAND, USB
This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos.
Posted in Data Center, Debug, DesignWare, events, NVMe, PCIe, Storage
With the rise of cloud computing and large scale data centers, both developers and consumers are demanding for more efficient ways to rapidly access their data. Seeing the advantage of its high performance, the storage industry is quickly adopting the Non-Volatile Memory Express (NVMe) standard. The NVMe™ standard continues to push the storage envelope with version 1.3 and beyond in all types of computing environments from mobile to data center. One of the key features of the NVMe™ standard is its ability to handle virtualization.
Posted in Data Center, events, NVMe, PCIe, Storage, Uncategorized
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM
PCIe is a multi-layered serial bus protocol which implements dual-simplex link. It provides high speed data transfer and low latency owing to its dedicated point to point topology. To accelerate verification and device development time for PCIe based sub-systems, PIPE (PHY Interface for the PCI Express) architecture was defined by Intel. PIPE is a standard interface defined between PHY sub-layer (PCS – Physical Coding sub-layer) and MAC (Media Access Layer).
Posted in Data Center, NVMe, PCIe, Storage
Is your latest NVMe design taking advantage of Streams? Adoption of this new NVMe technology is gaining momentum with Synopsys customers. Streams are part of the new, optional, Directives feature introduced in the NVMe 1.3 specification. Directives allow the passing of metadata between hosts and controllers via existing NVMe commands. Streams are unique in that they are the only I/O based Directive available in the 1.3 specification.
‘Big Data’, ‘IoT’, ‘Mobile’, ‘Networking’ and ‘Storage’ applications are the key drivers for next generation high-performance systems. To meet the bandwidth requirement of the emerging applications, it was required to either increase the lane width or speed. Increasing the lane width isn’t cost effective and thus increasing speed is the best viable option. PCIe 4.0 has doubled the per lane throughput to 16GT/s, compared to 8GT/s for PCIe 3.0, delivering higher performance without increasing the lane width.
During the recent PCI-SIG Developers Conference 2016, held in Santa Clara, CA, there was a lot of interest from attendees regarding Synopsys PCIe Gen4 VIP and source code test suite. One common question that was asked: How do we identify and maintain up to date tests that support the latest PCIe Gen4 specification?
Posted in Data Center, NVMe, PCIe, Processor Subsystems, Test Suites, Uncategorized
Synopsys recently announced the availability of industry’s first VIP to support the Serial-attached SCSI (SAS) 24G standard. Let’s look back how far we have come along, let’s time travel and re-live the interesting journey of storage and SCSI evolution.
