Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 CHI protocol – CHI Issue F (CHI-F). AMBA 5 CHI-F is built on top of the existing AMBA CHI Issue E (CHI-E) specification (read our blog on AMBA CHI-E here), and introduces several exciting features related to the latest Arm architecture and optimized transaction flows.
Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
CXL 3.0 Introduction Compute Express Link™ (CXL™) 3.0 is an open standard that defines high-speed cache-coherent interconnect and memory expander interconnect for CPU-to-device and CPU-to-memory connections. It is built on PCI Express® (PCIe®) 6.0 r1.0 specifications and leverages PCIe for physical and electrical interface. Artificial Intelligence (AI) and Machine Learning (ML) applications and widespread smart devices (e.g., autonomous vehicles) are driving factors behind exponentially rising requirements to build high-performing data center units that involve CPUs connected with accelerator processors, memory attached devices, and SmartNICs. These systems demand low latency requirements for CPU-attached devices to perform compute-intensive operations on massive data while maintaining coherency. To meet the increasing performance and scale requirements of these systems, the CXL Consortium has evolved its standard through the introduction of CXL 3.0. CXL 3.0 Specification Highlights
HDMI (High-Definition Multimedia Interface) is the most popular medium for transporting both audio and video information between two digital devices. In the past two decades, HDMI technology has evolved from HDMI 1.0 to HDMI 2.0. In 2017 HDMI 2.1 introduced enhanced gaming and media features such as Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM) to eliminate lag, stutter, and tearing, adding smoothness to the gaming and video experience. Recently the HDMI Forum has announced a new version, HDMI2.1a, that brings a standout gamer-friendly feature, Source-Based Tone Mapping (SBTM).
Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling – gathering, storing, moving, processing, and dispersing – pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.