The two fundamental requirements of every mobile device is speed and power, with the biggest challenge being that both are inversely proportional to each other. One simply cannot have both, because with higher speed comes higher power consumption. With the ever increasing demand for higher resolution graphics and media to enrich the user experience, there has been a significant addition to data processing that requires high speed data transfers. Even though the devices are capable of capturing and playing back high quality media, the storage unit is not fast enough to match the required transfer speeds. This is an out of sync combination and one of the biggest challenges for mobile designs. The problem here is that, a memory system is required to be capable enough to perform read write operations at high speed without adding any significant numbers to power consumption.
The DDR PHY Interface (DFI) is used in several consumer electronics devices including smart phones. DFI is an interface protocol that defines signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices, and between MC (Micro Controller) and PHY. DFI is applicable to all DRAM protocols including DDR4, DDR3, DDR2, DDR, LPDDR4, LPDDR3, LPDDR2 and LPDDR.
In today’s connected world of smart devices, we want to access our data faster and at the same time we want it to be secured and protected from intruders. Flash memories are not only faster but secured and reliable also in its avatar as UFS – Universal Flash Storage. This blog provides an insight into various security modes of UFS devices and how to access them. It also points out how encryption is used to secure the data further.
Flash memory first came into home with external storage devices (e.g. USB memory devices) at very modest capacities of few MB and have reached to hundreds of GB. Now it has become ubiquitous with applications across myriad of devices ranging from smart phones, to IoT, wearable and consumer electronics. With the explosion in applications, many flash memory protocols came into existence, and let’s talk about one of them – ONFi.
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |
Synopsys VC VIP provides Verdi Protocol Analyzer, a protocol and memory aware debug environment . In my previous blog Debugging Memory Protocols with the Verdi Protocol Analyzer, I discussed the value add for using the Verdi Protocol Analyzer to debug memory protocols easily and efficiently. Also, I described how easy it is to look at a specific command as a transaction rather than as interpreted signals. In this blog I’m going to show another feature that makes Verdi Protocol Analyzer the tool of choice for debugging memory protocol issues and for validating proper system behavior. Furthermore, the tool can be used for verification of the command sequencer and the interaction between the DUT and the memory models. The feature, we are going to look at today, is synchronizing transactions to the corresponding signals.
Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB |
Debug continues to be one of the biggest hurdles faced by design and verification engineers. While designing a system that requires close interactions with memories, engineers often rely on print statements or waveform viewers to decipher signal behaviors over time, and/or their relationship relative to other signals over time. While this kind of ad-hoc debugging helps in understanding the behavior of a single signal, it does not work well when debugging protocols.
My latest webinar, Keeping Pace with Memory Technology using Advanced Verification, begins by taking the audience back in time. To a time when memories had low density, slow performance, and required expensive silicon real estate. Then I fast forward back to the future when memory technologies have evolved to support huge densities, blazing fast speeds while keeping power consumption low, and all this within very small geometry.