VIP Central

Archive for the 'Memory' Category

 

First USB 3.2 VIP and TestSuite: Enhances the Verification Solution for USB IP, SoC and Type-C Subsystems

USB has literally become universal and present in every device ranging from smart phones and personal computers, IoT and wearables, storage and networking, consumer electronics and gaming consoles, automotive and many other emerging verticals. The success of USB can be attributed to innovation with each new generation—the capability to transfer data as well as supply power for charging devices and ease-of-use with a variety of connectors and form factors.

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Posted in Automotive, Data Center, Display, Flash, Mobile SoC, Storage, Type C, Uncategorized |

 

LPDDR4: The Total Package for Mobile SoC RAM

The mobile industry is growing at a very fast pace with its never-ending hunger for data and bandwidth. We have witnessed the change from a dial-pad to touch-screens, from black and white display to QHD 4k display with millions of colors, and memory space from KB to GB, in a very short span of time. The biggest challenge is increasing bandwidth without compromising performance or adding any significant numbers in the power consumption column. The solution to this challenge is the LPDDR or Mobile DDR standard released by JEDEC. There have been several revisions to this standard, the latest being LPDDR4. LPDDR4 provides a data bandwidth of 4266 Mbps, which is almost double that of LPDDR3. It also provides a significant reduction in power consumption compared to LPDDR3. For further insights on LPDDR4 and its predecessors please refer to our previous blog “LPDDR4: What Makes it Faster and Reduces Power Consumption.”

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Posted in DDR, LPDDR, Memory, Mobile SoC |

 

LPDDR4: What Makes It Faster and Reduces Power Consumption

DRAM memories are the ‘heart’ of any computational device, e.g. smart phones, laptops, servers etc. LPDDR4 was mainly designed to increase memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks.  It supports speeds up to 4267Mbps (double the speed of LPDDR3) and 1.1 V input/output buffer power, along with many other improvements compared to its predecessor (LPDDR3/LPDDR2). Below is a comparison of key features between all the three generations of LPDDR.

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Posted in Automotive, Data Center, DDR, DFI, LPDDR, Memory, Mobile SoC |

 

Flavors of SPI: Emerging Protocol in Automotive

SPI interface is emerging as a popular choice in automotive applications ranging from sensors, display console, navigation systems, booting through SPI Flash and many more. SPI low pin count and configurable clock rate facilitate the requirements of the emerging automotive applications.

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Posted in Automotive, Flash, Memory, SPI |

 

Next Generation Memory technologies: Ready to take the verification challenges?

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Posted in Data Center, DDR, Debug, DFI, eMMC, events, Flash, HBM, HMC, LPDDR, Memory, ONFi, Storage, UFS |

 

eMMC: An Optimal Flash Memory

The two fundamental requirements of every mobile device is speed and power, with the biggest challenge being that both are inversely proportional to each other. One simply cannot have both, because with higher speed comes higher power consumption. With the ever increasing demand for higher resolution graphics and media to enrich the user experience, there has been a significant addition to data processing that requires high speed data transfers. Even though the devices are capable of capturing and playing back high quality media, the storage unit is not fast enough to match the required transfer speeds.  This is an out of sync combination and one of the biggest challenges for mobile designs. The problem here is that, a memory system is required to be capable enough to perform read write operations at high speed without adding any significant numbers to power consumption.

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Posted in Automotive, eMMC, Flash, Memory, Mobile SoC, Uncategorized |

 

DDR-PHY Interoperability Using DFI

The DDR PHY Interface (DFI) is used in several consumer electronics devices including smart phones. DFI is an interface protocol that defines signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices, and between MC (Micro Controller) and PHY. DFI is applicable to all DRAM protocols including DDR4, DDR3, DDR2, DDR, LPDDR4, LPDDR3, LPDDR2 and LPDDR.

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Posted in DDR, DFI, LPDDR, Uncategorized |

 

UFS – Faster and Secured Flash Storage

In today’s connected world of smart devices, we want to access our data faster and at the same time we want it to be secured and protected from intruders. Flash memories are not only faster but secured and reliable also in its avatar as UFS – Universal Flash Storage. This blog provides an insight into various security modes of UFS devices and how to access them. It also points out how encryption is used to secure the data further.

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Posted in Flash, Memory, MIPI, UFS, Unipro |

 

Racing Ahead with ONFI 1 to 4: 50 to 800MBps

Flash memory first came into home with external storage devices (e.g. USB memory devices) at very modest capacities of few MB and have reached to hundreds of GB. Now it has become ubiquitous with applications across myriad of devices ranging from smart phones, to IoT, wearable and consumer electronics. With the explosion in applications, many flash memory protocols came into existence, and let’s talk about one of them –  ONFi.

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Posted in Flash, ONFi |

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |