Flash storage is one of the most important component of a smart phone, and with every new version comes higher memory capacity and performance. The most rapidly adopted flash memory technology in recent years is Universal Flash Storage (UFS), with UFS v2.1 providing a maximum data rate of ~11Gbps. JEDEC has come up with the faster next-generation UFS v3.0 which uses MIPI UniPro v1.8 (Unified Protocol) and MIPI M-PHY v4.1 as interconnect layer.
New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency. Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.” Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.
SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM |
Safety features have always been important in the automotive industry; it has certainly become the most critical requirement for autonomous vehicles. Have you ever wondered what technology makes it possible for multiple sensors located at front, rear sections and inside the doors to work in a coordinated manner for early crash detection and operate the vehicles air bags thereby protecting precious human life?
In this era of revolutionary technologies, memory plays a vital role in any application that requires high-speed processing. High-resolution graphics require high-speed and high-bandwidth graphics memory, resulting in rapid adoption of next generation memory technology High-Bandwidth Memory (HBM). HBM is finding its way into leading-edge graphics, networking, HPC (High Performance Computing), and Artificial Intelligence systems; for example, decoders for a video signal, fully autonomous vehicles, neural network designs, and other advanced applications that demand low power and massive bandwidth. Our previous memory blog – Next generation memory technologies: Ready to take the verification challenges?, discussed several next generation memory technologies across applications. This blog will review the details of HBM, a next generation memory technology for graphics, networking and HPC.
Higher storage performance at a lower cost can create a bottleneck in the design of storage devices. In order to achieve higher performance, devices must use on chip DRAM, which adds to the overall cost. This is where Unified Memory Extension (UME), a JEDEC specification, comes into the picture. It is defined as extension to the JEDEC UFS (Universal Flash Storage) specification. JEDEC UFS device uses NAND flash technology for data storage. Unified Memory (UM) allows users to use part of the host memory as the device’s internal memory. Since the host memory is already available in large capacities, this mechanism provides a much bigger space for the device to use as a Write Buffer (WB) cache or to store information such as Logical to Physical (L2P) address translation tables. The UM area is physically located on the host side but ultimately belongs to the device, thereby replacing the device-integrated RAM, and reducing overall cost. Large space availability means the device can store larger amounts of WB of L2P table information resulting in higher storage performance.
First USB 3.2 VIP and TestSuite: Enhances the Verification Solution for USB IP, SoC and Type-C Subsystems
USB has literally become universal and present in every device ranging from smart phones and personal computers, IoT and wearables, storage and networking, consumer electronics and gaming consoles, automotive and many other emerging verticals. The success of USB can be attributed to innovation with each new generation—the capability to transfer data as well as supply power for charging devices and ease-of-use with a variety of connectors and form factors.
The mobile industry is growing at a very fast pace with its never-ending hunger for data and bandwidth. We have witnessed the change from a dial-pad to touch-screens, from black and white display to QHD 4k display with millions of colors, and memory space from KB to GB, in a very short span of time. The biggest challenge is increasing bandwidth without compromising performance or adding any significant numbers in the power consumption column. The solution to this challenge is the LPDDR or Mobile DDR standard released by JEDEC. There have been several revisions to this standard, the latest being LPDDR4. LPDDR4 provides a data bandwidth of 4266 Mbps, which is almost double that of LPDDR3. It also provides a significant reduction in power consumption compared to LPDDR3. For further insights on LPDDR4 and its predecessors please refer to our previous blog “LPDDR4: What Makes it Faster and Reduces Power Consumption.”
DRAM memories are the ‘heart’ of any computational device, e.g. smart phones, laptops, servers etc. LPDDR4 was mainly designed to increase memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. It supports speeds up to 4267Mbps (double the speed of LPDDR3) and 1.1 V input/output buffer power, along with many other improvements compared to its predecessor (LPDDR3/LPDDR2). Below is a comparison of key features between all the three generations of LPDDR.