The key features driving future memories are memory density, speed, lower operating voltage, and faster access. DDR5 supports memory density from 8Gb to 64Gb combined with a wide range of data rate from 3200 MT/s to 6400 MT/s. The operating voltage of DDR5 is further reduced from 1.2V of DDR4 to 1.1V.
Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.
We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance analyzer and protocol debug. In case you missed the latest buzz on Verification IP, you can read it here.
The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has evolved along with the memory technologies, and next generation DFI 5.0 is here to ensure higher performance in the systems using DDR5/LPDDR5. In this blog, we will discuss the new features of DFI 5.0 specification.
High speed memory interface is a critical component to support high speed data in applications like personal computers, mobile phones, and digital cameras. These applications require a high capacity and high performance NAND flash memory, and Toggle2NAND is one of the most suitable NAND interfaces.
In today’s world of smartphones and tablets, high speed data at low power consumption is becoming increasingly important. MIPI M-PHY supports multiple applications with high data bandwidth and low power consumption which makes it a popular specification for mobile devices. Applications like JEDEC UFS 3.0 and MIPI UniPro 1.8 now support MIPI M-PHY 4.1 which provides high speed data at a rate of nearly 11Gbps (HS_G4). To learn more about latest UFS and UniPro specifications read our previous blog “High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0”. Data at such a high speed can lead to inter-symbol-interference (ISI). M-PHY provides a safety measure to prevent the loss of data at HS_G4. In this blog, we are going to talk about the ‘ADAPT’ feature and its advantages which were introduced in M-PHY 4.0.
Flash storage is one of the most important component of a smart phone, and with every new version comes higher memory capacity and performance. The most rapidly adopted flash memory technology in recent years is Universal Flash Storage (UFS), with UFS v2.1 providing a maximum data rate of ~11Gbps. JEDEC has come up with the faster next-generation UFS v3.0 which uses MIPI UniPro v1.8 (Unified Protocol) and MIPI M-PHY v4.1 as interconnect layer.
New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency. Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.” Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.
SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM