VIP Central

Archive for the 'LPDDR' Category

 

A New Generation of LPDDR

Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.

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Posted in LPDDR

 

Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings

We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.

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Posted in LPDDR, Memory, Uncategorized

 

LPDDR5: Meeting Power, Performance, Bandwidth, and Reliability Requirements of AI, IoT and Automotive

The semiconductor industry is buzzing with new technologies – Artificial Intelligence (AI), Machine Learning (ML), IoT, Automotive, etc. – bringing a revolution by easing out our day-to-day lives and improving considerably performance, bandwidth and reliable data processing and transfer. Reliability and data integrity are even more important for safety critical verticals where even the slightest error can be catastrophic. Stepping up to meet industry trends, JEDEC recently announced its fifth revision of LPDDR standard JESD209-5 which is all equipped to match the latest bandwidth, power, performance, and reliability trends. Immediately following this, Synopsys announced the Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5. Strengthening our leadership in memory VIP, recently we also announced the Industry’s First DDR5 NVDIMM-P Verification IP, showing our continued collaboration with leading memory vendors.

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Posted in AI, Automotive, IoT, LPDDR, Memory, Uncategorized

 

Latest Buzz on Next Generation Protocols – USB4, PCIe 5.0, LPDDR5, and DDR5

We recently published the VIP Newsletter for Apr 2019, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in Data Center, DDR, Debug, LPDDR, Memory, Mobile SoC, PCIe, Processor Subsystems, Test Suites, Type C, USB

 

Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5

Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.

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Posted in Automotive, Data Center, DDR, Debug, DesignWare, DFI, HBM, LPDDR, Memory, Mobile SoC

 

Trending Articles on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, and PCIe 5.0

We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance analyzer and protocol debug. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in Automotive, Camera, CSI, Data Center, DDR, Debug, DFI, Display, DisplayPort, DSC, events, Flash, HDMI, LPDDR, Memory, MIPI, Mobile SoC, NVMe, PCIe, Storage, Test Suites, ToggleNAND, USB

 

How DFI 5.0 Ensures Higher Performance in DDR5/LPDDR5 Systems?

The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has evolved along with the memory technologies, and next generation DFI 5.0 is here to ensure higher performance in the systems using DDR5/LPDDR5. In this blog, we will discuss the new features of DFI 5.0 specification.

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Posted in Automotive, Data Center, DDR, DFI, LPDDR, Memory, Storage

 

LPDDR5: Enhancements in Bandwidth, Reliability, and Power for IoT, AI, and Image Processing

New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency.  Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.”  Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.

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Posted in Automotive, Camera, DDR, DFI, Display, HBM, HMC, LPDDR, Memory, Mobile SoC

 

Bye Bye Bottlenecks – Automated SoC Performance Verification is Here!

SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?

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Posted in Automotive, Data Center, DDR, DFI, events, HBM, LPDDR, Memory, Uncategorized

 

Latest Buzz on Next Generation Protocols

We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM