VIP Central

Archive for the 'LPDDR' Category

 

LPDDR4: What Makes It Faster and Reduces Power Consumption

DRAM memories are the ‘heart’ of any computational device, e.g. smart phones, laptops, servers etc. LPDDR4 was mainly designed to increase memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks.  It supports speeds up to 4267Mbps (double the speed of LPDDR3) and 1.1 V input/output buffer power, along with […]

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Posted in Automotive, Data Center, DDR, DFI, LPDDR, Memory, Mobile SoC | No Comments »

 

Next Generation Memory technologies: Ready to take the verification challenges?

Advancement in Memory technologies and the demand for faster and higher density configuration leaves verification engineers in a limbo. The Memory world is debating the next wave of memory protocols and technologies such as Next Generation DDR, HBM, and NVDIMM: DDR: Wishfully the next generation DDR specifications will bring many benefits to computers. With faster and […]

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Posted in Data Center, DDR, Debug, DFI, eMMC, events, Flash, HBM, HMC, LPDDR, Memory, ONFi, Storage, UFS | Comments Off on Next Generation Memory technologies: Ready to take the verification challenges?

 

DDR-PHY Interoperability Using DFI

The DDR PHY Interface (DFI) is used in several consumer electronics devices including smart phones. DFI is an interface protocol that defines signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices, and between MC (Micro Controller) and PHY. DFI is applicable to all DRAM protocols including […]

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Posted in DDR, DFI, LPDDR, Uncategorized | Comments Off on DDR-PHY Interoperability Using DFI

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event. Synopsys hosted the annual “SoC Leaders Verify with Synopsys” Verification luncheon.  The luncheon featured industry experts and executives from Cavium, NXP, Qualcomm and Samsung, and drove our main messages of collaboration, with […]

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM | Comments Off on Verification Highlights from DAC 2016

 

Simplifying Debug of Memory Models

Synopsys VC VIP provides Verdi Protocol Analyzer, a protocol and memory aware debug environment . In my previous blog Debugging Memory Protocols with the Verdi Protocol Analyzer, I discussed the value add for using the Verdi Protocol Analyzer to debug memory protocols easily and efficiently. Also, I described how easy it is to look at a specific command […]

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Posted in DDR, Debug, DFI, Flash, HBM, HMC, LPDDR, Memory, Uncategorized | Comments Off on Simplifying Debug of Memory Models

 

Celebrating the Holiday Season with VIPs

The Holiday Season is upon us. As you stand in lines, wait for packages to arrive, keep in mind that Synopsys continues to provide you the highest level of service: support, available protocols and deployment of new titles that you, our current and future VIP customer, deserve. It has been a wonderful year — many […]

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Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB | Comments Off on Celebrating the Holiday Season with VIPs

 

Keeping Pace with Memory Technology using Advanced Verification

My latest webinar, Keeping Pace with Memory Technology using Advanced Verification, begins by taking the audience back in time. To a time when memories had low density, slow performance, and required expensive silicon real estate. Then I fast forward back to the future when memory technologies have evolved to support huge densities, blazing fast speeds while […]

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Posted in DDR, DFI, Flash, HBM, HMC, LPDDR | Comments Off on Keeping Pace with Memory Technology using Advanced Verification

 

Seamless Fast Initialization for DDR VIP Models

DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. Here we will discuss fast initialization for DDR VIP models. You can learn more about Synopsys Memory VIP here. As per the […]

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Posted in DDR, LPDDR, Memory, Processor Subsystems | Comments Off on Seamless Fast Initialization for DDR VIP Models

 

Increase Productivity with Synopsys Memory VIP

In this video, you will learn how to increase productivity with Synopsys Memory VIP. You can learn more about our VIPs at Verification IP Overview. If you are interested in a hands-on workshop in your area, check out our Memory Verification IP Workshops.

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Posted in DDR, Debug, DFI, eMMC, Flash, HBM, HMC, LPDDR, Memory, Methodology, ONFi, UFS, UVM | Comments Off on Increase Productivity with Synopsys Memory VIP

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans. You can learn more […]

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM | Comments Off on Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP