In the blog Seamless Fast Initialization for DDR VIP Models, we discussed how important it is for Memory VIP simulations to have the option of going through the process of Reset and Initialization fast, and get to the IDLE state and start reading and writing to memory location. We presented one way to achieve this by scaling down the timings required while going thru all the JEDEC standard steps required for Reset and Initialization.
DDR verification is one of the most critical and complex tasks in any SoC as it involves a controller sitting inside the DUT and an external DDR memory sitting outside the DUT on board. Here we will discuss fast initialization for DDR VIP models.
In this video, you will learn how to increase productivity with Synopsys Memory VIP.
Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.
Synopsys Memory Verification IP is modeled natively in SystemVerilog and supports the common verification standard UVM. Our models support 100% of the memory standard as specified by JEDEC.
Here, Synopsys Applications Consultant, Vaish Ramachandran, describes how best we can use Synopsys’ VIP Configuration Creator for configuring memory VIPs http://bit.ly/1JcvSII
Behavioral Memory Models have been used for verification purposes for several years now. In the early days, modeling technology didn’t add much value to the usage model as designs were simple.
At DVCon 2015, a couple of our key customers shared their viewpoints on how they manage growing verification complexity. This video begins with Michael Sanie highlighting the Synopsys Verification Continuum, and several key technologies that currently address the industry’s need to “Shift-Left” for faster time-to-market. Later, Amol Bhinge of Freescale and Prashanth Gurunath of Xilinx share how their leading SoC design teams have achieved success by collaborating with Synopsys.
Following on his recent talk about Key Advantages of Synopsys Memory VIP Architecture, here Synopsys R&D Director Bernie DeLay talks about protocol-aware debug for memories: a single environment to simultaneously visualize transactions, state machines, and memory arrays http://bit.ly/1KKRmMn
Following on his recent talk about why Synopsys chose a SystemVerilog Architecture for interface VIP, here Synopsys R&D Director Bernie DeLay talks about how a similar architecture based on SystemVerilog for Memory VIP brings some key advantages for verifying the memory interfaces in your SoC design and memory controller IP: http://bit.ly/1zaAcip