The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.
We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
Servers are the core of today’s computational world, processing and storing data on multi-user platforms. Server performance depends on latency and capacity of its memory and storage. In general, DDR-DIMMs (Double Data Rate Dual In-line Memory Modules) are used as server memory, whereas SSDs/HDDs are used as storage in server. Whenever a service request is made to the server, it may require both data processing and storage. In order to execute this service, the processor accesses DDR-DIMMs and SSDs/HDDs. In addition, SSDs/HDDs can be accessed in case of power loss, storing data using backup power sources so data can be retrieved once power is available again.
Modern computer applications rely heavily on graphics processing and rendering which involve a lot of simultaneous mathematical calculations. A typical CPU is not suitable for jobs that require simultaneous processing, which is why the concept of a dedicated Graphics Processing Unit (GPU) was introduced. The GPU has found its scope not only in graphics processing but also several emerging applications like AI, machine learning, VR, autonomous driving, and network routing.
LPDDR5: Meeting Power, Performance, Bandwidth, and Reliability Requirements of AI, IoT and Automotive
The semiconductor industry is buzzing with new technologies – Artificial Intelligence (AI), Machine Learning (ML), IoT, Automotive, etc. – bringing a revolution by easing out our day-to-day lives and improving considerably performance, bandwidth and reliable data processing and transfer. Reliability and data integrity are even more important for safety critical verticals where even the slightest error can be catastrophic. Stepping up to meet industry trends, JEDEC recently announced its fifth revision of LPDDR standard JESD209-5 which is all equipped to match the latest bandwidth, power, performance, and reliability trends. Immediately following this, Synopsys announced the Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5. Strengthening our leadership in memory VIP, recently we also announced the Industry’s First DDR5 NVDIMM-P Verification IP, showing our continued collaboration with leading memory vendors.
We recently published the VIP Newsletter for Apr 2019, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
The key features driving future memories are memory density, speed, lower operating voltage, and faster access. DDR5 supports memory density from 8Gb to 64Gb combined with a wide range of data rate from 3200 MT/s to 6400 MT/s. The operating voltage of DDR5 is further reduced from 1.2V of DDR4 to 1.1V.
Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.