NAND Flash Memory – Key Element For Your Multi-Die System Verification – Part-1
Introduction to NAND Flash Memory
Utilize Advanced RPMB for Faster and More Secure UFS 4.0 Authentication
In a 5G world, fast and secure connectivity is important. The JEDEC Universal Flash Storage (UFS) version 4.0 helps to ensure this is possible in our everyday devices. As an added security element, a Replay Protected Memory Block (RPMB) is included in UFS devices as a means to store encrypted data securely, only accessible by authentication.
LPDDR5X – An Extension to LPDDR5 for Future Mobile System
Emerging technologies such as Internet of Things (IoT), 5G, Automotive, Artificial Intelligence (AI), and High-Performance Computing, have given rise to potentially transformative trends demanding the need for faster memory access. 5G brings with itself the ability for faster download and upload speeds, making high-speed real-time data transfer possible. All the fancy smartphone processors have inbuilt cutting-edge features like high resolution multimedia processing, faster Machine Learning (ML) computations, Image processing capabilities and faster frame rates for all you gaming freaks. But don’t forget underlying all this, is the need for faster memory, AI/ML requires higher bandwidth to support faster processing of massive data.
Accelerate SoC Verification, Experts available
SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.
Posted in ACE, AMBA, CXL, Debug, Display, Ethernet, HBM, Memory, Test Suites, Verification Service
The wait is over – JEDEC Announces JESD79-5, DDR5 SDRAM VIP for High Performance Computing
JEDEC recently announced the ratification of JESD79-5 DDR5 SDRAM to support the standardization of next-generation memory devices, catering to demand from rapid expansion in high performance computing and data center applications. This new standard promises to deliver 2X memory bandwidth, 4X larger density dies, and much improved power efficiency (1.1V Vdd). The DDR5 DIMM will operate in dual-channel mode all on its own, with two 40-bit fully independent sub-channels on the same module.
A New Generation of LPDDR
Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.
Posted in LPDDR
DDR5 – Off and Running
The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.
Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings
We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.
Posted in LPDDR, Memory, Uncategorized
How to Reduce Memory Model Debug Time
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
Posted in Debug, Memory, Uncategorized
