Arm TechCon 2017 took place at Santa Clara on 24-26th Oct, 2017. This year, Synopsys’ Arm® AMBA® protocol experts were on hand to demonstrate our verification automation solutions for Arm AMBA Coherent Interconnects. Synopsys Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances. Our experts also introduced our AMBA AutoPerformance solution to generate AMBA(CHI/ACE/AXI) interconnect performance verification stimulus. The AutoPerformance solution, based on Arm traffic profile specification, enables user to define traffic profiles for measurement of performance metrics like throughput, latency etc., and the stimulus is driven by VIP for AMBA (CHI/ACE/AXI).
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Posted in ACE, AMBA, Automotive, CCI400, CHI, Data Center, Interconnects, Methodology, Mobile SoC, NOC, Processor Subsystems, SystemVerilog, Test Suites, UVM
Synopsys hosted the annual Verification Luncheon and Customer Panel – SoC Leaders Verify with Synopsys at DAC 2017 in Austin, Texas. The panel featured industry experts and executives from Intel, Qualcomm, AMD, NXP, and Wave Computing, and drove our main messages of innovation and technology leadership, in addition to collaborations with market makers. In case you missed it, this blog provides the highlights and video of the event.
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Posted in ACE, AMBA, CCI400, CHI, events, Interconnects
There was a time when coherent multi-processor systems were a niche technology with complex proprietary architectures. With ever increasing demand for performance, coherent systems with multiple processors and coherent accelerators are now being adopted rapidly across applications and market segments ranging from infrastructure networking and servers to storage and automotive. ARM® AMBA® 5 CHI provides the much needed standard architecture for coherent designs.
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Posted in ACE, AMBA, CCI400, CHI, Interconnects, NOC, Processor Subsystems
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Posted in ACE, AMBA, Automotive, CAN, CCI400, CHI, Data Center, Display, DisplayPort, eMMC, Ethernet AVB, FlexRay, HDCP, Interconnects, JESD, LIN, MIPI, PCIe, Processor Subsystems, UFS
The ordering of memory transactions in Arm® AMBA® protocol is a significant requirement, i.e. the sequence of memory updates/accesses must follow a defined ordering as per the specification. Ordering is important for synchronization events by a processor with respect to retiring load/store instructions. AMBA ACE barrier transactions are used for maintaining the memory ordering across a system. The learning curve to understand barrier transactions may become a barrier to verify your design thoroughly. This blog provides insight, making it easier to understand and verify the barrier transactions. The blog will cover different types of barrier transactions, usage, and domain boundaries.
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Posted in ACE, AMBA, CCI400, CHI, Interconnects, Test Suites, Uncategorized
AMBA AXI exclusive access may look simple at first glance, but as we delve deeper into it, we find the different flavors of exclusive access. The possibility of these different scenarios and combinations poses a tough challenge in verifying the critical feature in AMBA-based designs. This blog primarily focusses on exclusive access in AMBA AXI3, the concept, its different flavors and how Synopsys VIP can be leveraged to overcome the corresponding verification challenges.
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Posted in AMBA, CCI400, Interconnects, NOC, Test Suites, Uncategorized
