VIP Central

Archive for the 'CCI400' Category

 

SoC Leaders Verify with Synopsys: Watch it Now

Synopsys hosted the annual Verification Luncheon and Customer Panel – SoC Leaders Verify with Synopsys at DAC 2017 in Austin, Texas. The panel featured industry experts and executives from Intel, Qualcomm, AMD, NXP, and Wave Computing, and drove our main messages of innovation and technology leadership, in addition to collaborations with market makers. In case you missed it, […]

Continue Reading...

Posted in ACE, AMBA, CCI400, CHI, events, Interconects | Comments Off on SoC Leaders Verify with Synopsys: Watch it Now

 

Rapid Adoption of Synopsys VIP for ARM AMBA 5 CHI

There was a time when coherent multi-processor systems were a niche technology with complex proprietary architectures. With ever increasing demand for performance, coherent systems with multiple processors and coherent accelerators are now being adopted rapidly across applications and market segments ranging from infrastructure networking and servers to storage and automotive. ARM® AMBA® 5 CHI provides […]

Continue Reading...

Posted in ACE, AMBA, CCI400, CHI, Interconects, NOC, Processor Subsystems | Comments Off on Rapid Adoption of Synopsys VIP for ARM AMBA 5 CHI

 

Latest Buzz in Verification IP

    We recently released the Q2 VIP newsletter containing trending topics, leading solutions, in depth technical articles, videos, webinars and product announcements from VIP and protocol experts. In case you missed the latest buzz on Verification IP, you can read it here.                         […]

Continue Reading...

Posted in ACE, AMBA, Automotive, CAN, CCI400, CHI, Data Center, Display, DisplayPort, eMMC, Ethernet AVB, FlexRay, HDCP, Interconects, JESD, LIN, MIPI, PCIe, Processor Subsystems, UFS | Comments Off on Latest Buzz in Verification IP

 

Jumping the Barrier of Verifying AMBA ACE Barrier Transactions

The ordering of memory transactions in AMBA protocol is a significant requirement, i.e. the sequence of memory updates/accesses must follow a defined ordering as per the specification. Ordering is important for synchronization events by a processor with respect to retiring load/store instructions. AMBA ACE barrier transactions are used for maintaining the memory ordering across a […]

Continue Reading...

Posted in ACE, AMBA, CCI400, CHI, Interconects, Test Suites, Uncategorized | Comments Off on Jumping the Barrier of Verifying AMBA ACE Barrier Transactions

 

AMBA AXI Exclusive Access De-mystified

AMBA AXI exclusive access may look simple at first glance, but as we delve deeper into it, we find the different flavors of exclusive access. The possibility of these different scenarios and combinations poses a tough challenge in verifying the critical feature in AMBA-based designs. This blog primarily focusses on exclusive access in AMBA AXI3, […]

Continue Reading...

Posted in AMBA, CCI400, Interconects, NOC, Test Suites, Uncategorized | 1 Comment »