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Archive for the 'Interconects' Category

 

Jumping the Barrier of Verifying AMBA ACE Barrier Transactions

The ordering of memory transactions in AMBA protocol is a significant requirement, i.e. the sequence of memory updates/accesses must follow a defined ordering as per the specification. Ordering is important for synchronization events by a processor with respect to retiring load/store instructions. AMBA ACE barrier transactions are used for maintaining the memory ordering across a […]

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Posted in ACE, AMBA, CCI400, CHI, Interconects, Test Suites, Uncategorized | Comments Off on Jumping the Barrier of Verifying AMBA ACE Barrier Transactions

 

AMBA AXI Exclusive Access De-mystified

AMBA AXI exclusive access may look simple at first glance, but as we delve deeper into it, we find the different flavors of exclusive access. The possibility of these different scenarios and combinations poses a tough challenge in verifying the critical feature in AMBA-based designs. This blog primarily focusses on exclusive access in AMBA AXI3, […]

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Posted in AMBA, CCI400, Interconects, NOC, Test Suites, Uncategorized | 1 Comment »

 

Debug of AMBA AXI Outstanding Transactions

Verifying today’s complex designs is time consuming, as simulations run for long time and millions of transaction are executed. Traditional approach of debug is to dump all the information of millions of packets in a log file, however it would always be challenging to filter out specific transactions from the huge log file. For example, […]

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Posted in AMBA, Debug, Interconects | Comments Off on Debug of AMBA AXI Outstanding Transactions

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event. Synopsys hosted the annual “SoC Leaders Verify with Synopsys” Verification luncheon.  The luncheon featured industry experts and executives from Cavium, NXP, Qualcomm and Samsung, and drove our main messages of collaboration, with […]

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM | Comments Off on Verification Highlights from DAC 2016

 

ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug

Companies developing complex ARM-based SoC designs have to constantly keep up with evolving interface standards and proliferating protocols a recurring problem that is resource-intensive and time-consuming. Orchestrating these multiple protocols is critical to extracting maximum SoC performance a key competitive differentiator. Achieving high performance while ensuring correct protocol behavior is best addressed by a combination […]

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Posted in AMBA, CHI, Debug, Methodology | Comments Off on ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug