In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively?
In my previous blog, AMBA based Subsystems: What does it take to verify them?, I had discussed some of the key verification challenges when it comes to verifying complex SOCs based on AMBA based subsystems. It was observed that it would indeed be useful to have an extensible AMBA based verification environment which can be tweaked minimally so that it can be reused for new systems or derivatives.
VIP manager Tushar Mattu of Synopsys describes how to program AXI-ACE VIP to generate error scenarios
VIP manager Tushar Mattu of Synopsys gives insights on how to effectively integrate uvm_reg with AXI VIP http://bit.ly/1xboMLS
Recently I worked with a user who was responsible for verifying an AXI interface. This user did not have a UVM background, but was conversant with SystemVerilog. The user was faced with the challenge of learning UVM as well as coming up to speed with an understanding of the VIP: both at the same time, under tight verification timelines. Figuring out how much UVM knowledge would suffice to integrate the VIP, then coding the testbench around the VIP to run and debug the verification environment, appeared to be the first few challenges. I proposed a simple approach: let us begin with a simple directed testbench, get some AXI tests going using the VIP, gain some confidence in terms of understanding the core functionality of the DUT and VIP, and then, in parallel, learn some UVM basics as well. Later, I suggested, he can move on to advanced testing using constrained-random verification where he will need more advanced UVM knowledge, for instance, the application of virtual sequences.
VIP manager Tushar Mattu of Synopsys gives insights on how to effectively use the AXI VIP Debug Port http://bit.ly/18QYPMs
Here, Synopsys VIP manager Tushar Mattu describes how best we can integrate AXI VIP into a UVM Testbench: http://bit.ly/1Ay3zfb
Let’s look at a typical AMBA based subsystem in the SOCs that we find today:
Following on his recent talk about Key Advantages of Synopsys Memory VIP Architecture, here Synopsys R&D Director Bernie DeLay talks about protocol-aware debug for memories: a single environment to simultaneously visualize transactions, state machines, and memory arrays http://bit.ly/1KKRmMn
In the last post of this series, I wrote about basic coherent testing. In this post, I will discuss some of the nuances of the specification relative to accesses to overlapping addresses. Since multiple masters may be sharing the same location and the data could be distributed across the caches of different masters, this is an important part of the verification of a coherent system. The interconnect plays a very important role in maintaining coherency for such accesses.
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