Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.
SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.
Synopsys offers a broad set of verification solutions for next-generation AMBA® protocols, including AMBA CXS. Synopsys also has verification automation solutions for Arm-based protocols including VC AutoTestbench for testbench generation and VC AutoPerformance for performance verification.
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.
We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM
Industry’s First Source Code Test Suite and Verification IP for Arm AMBA ACE5 and AXI5 Enables Early Adopter Success
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA CHI Issue B, and verification automation solutions including Auto SoC Testbench Generation and AutoPerformance for AMBA protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of source code test suites and VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications.
Ever since Arm released the Arm® AMBA® 5 AHB5 protocol specifications, questions have arisen among users in the design and verification community—”Why AHB5?”, “What is new in AHB5?” etc. This post initiates a short series of blogs in which we will address these questions and introduce the new features of AMBA 5 AHB5.
Arm TechCon 2017 took place at Santa Clara on 24-26th Oct, 2017. This year, Synopsys’ Arm® AMBA® protocol experts were on hand to demonstrate our verification automation solutions for Arm AMBA Coherent Interconnects. Synopsys Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances. Our experts also introduced our AMBA AutoPerformance solution to generate AMBA(CHI/ACE/AXI) interconnect performance verification stimulus. The AutoPerformance solution, based on Arm traffic profile specification, enables user to define traffic profiles for measurement of performance metrics like throughput, latency etc., and the stimulus is driven by VIP for AMBA (CHI/ACE/AXI).