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Archive for the 'Processor Subsystems' Category

 

Higher Mobile Storage Performance at Lower System Cost

Higher storage performance at a lower cost can create a bottleneck in the design of storage devices.  In order to achieve higher performance, devices must use on chip DRAM, which adds to the overall cost. This is where Unified Memory Extension (UME), a JEDEC specification, comes into the picture. It is defined as extension to […]

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Posted in Automotive, eMMC, Flash, Memory, MIPI, Mobile SoC, ONFi, SPI, Storage, UFS, Uncategorized, Unipro | No Comments »

 

Verification Automation Solutions for Arm AMBA Coherent Interconnects

Arm TechCon 2017 took place at Santa Clara on 24-26th Oct, 2017. This year, Synopsys’ Arm® AMBA® protocol experts were on hand to demonstrate our verification automation solutions for Arm AMBA Coherent Interconnects. Synopsys Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and […]

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Posted in ACE, AMBA, Automotive, CCI400, CHI, Data Center, Interconects, Methodology, Mobile SoC, NOC, Processor Subsystems, SystemVerilog, Test Suites, UVM | No Comments »

 

First USB 3.2 VIP and TestSuite: Enhances the Verification Solution for USB IP, SoC and Type-C Subsystems

USB has literally become universal and present in every device ranging from smart phones and personal computers, IoT and wearables, storage and networking, consumer electronics and gaming consoles, automotive and many other emerging verticals. The success of USB can be attributed to innovation with each new generation—the capability to transfer data as well as supply […]

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Posted in Automotive, Data Center, Display, Flash, Mobile SoC, Storage, Type C, Uncategorized | No Comments »

 

LPDDR4: The Total Package for Mobile SoC RAM

The mobile industry is growing at a very fast pace with its never-ending hunger for data and bandwidth. We have witnessed the change from a dial-pad to touch-screens, from black and white display to QHD 4k display with millions of colors, and memory space from KB to GB, in a very short span of time. […]

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Posted in DDR, LPDDR, Memory, Mobile SoC | Comments Off on LPDDR4: The Total Package for Mobile SoC RAM

 

LPDDR4: What Makes It Faster and Reduces Power Consumption

DRAM memories are the ‘heart’ of any computational device, e.g. smart phones, laptops, servers etc. LPDDR4 was mainly designed to increase memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks.  It supports speeds up to 4267Mbps (double the speed of LPDDR3) and 1.1 V input/output buffer power, along with […]

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Posted in Automotive, Data Center, DDR, DFI, LPDDR, Memory, Mobile SoC | Comments Off on LPDDR4: What Makes It Faster and Reduces Power Consumption

 

Flavors of SPI: Emerging Protocol in Automotive

SPI interface is emerging as a popular choice in automotive applications ranging from sensors, display console, navigation systems, booting through SPI Flash and many more. SPI low pin count and configurable clock rate facilitate the requirements of the emerging automotive applications. Synchronous Serial Peripheral bus (SPI) allows synchronous serial communication between a controller and peripheral […]

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Posted in Automotive, Flash, Memory, SPI | Comments Off on Flavors of SPI: Emerging Protocol in Automotive

 

SoC Leaders Verify with Synopsys: Watch it Now

Synopsys hosted the annual Verification Luncheon and Customer Panel – SoC Leaders Verify with Synopsys at DAC 2017 in Austin, Texas. The panel featured industry experts and executives from Intel, Qualcomm, AMD, NXP, and Wave Computing, and drove our main messages of innovation and technology leadership, in addition to collaborations with market makers. In case you missed it, […]

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Posted in ACE, AMBA, CCI400, CHI, events, Interconects | Comments Off on SoC Leaders Verify with Synopsys: Watch it Now

 

Rapid Adoption of Synopsys VIP for ARM AMBA 5 CHI

There was a time when coherent multi-processor systems were a niche technology with complex proprietary architectures. With ever increasing demand for performance, coherent systems with multiple processors and coherent accelerators are now being adopted rapidly across applications and market segments ranging from infrastructure networking and servers to storage and automotive. ARM® AMBA® 5 CHI provides […]

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Posted in ACE, AMBA, CCI400, CHI, Interconects, NOC, Processor Subsystems | Comments Off on Rapid Adoption of Synopsys VIP for ARM AMBA 5 CHI

 

Latest Buzz in Verification IP

    We recently released the Q2 VIP newsletter containing trending topics, leading solutions, in depth technical articles, videos, webinars and product announcements from VIP and protocol experts. In case you missed the latest buzz on Verification IP, you can read it here.                         […]

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Posted in ACE, AMBA, Automotive, CAN, CCI400, CHI, Data Center, Display, DisplayPort, eMMC, Ethernet AVB, FlexRay, HDCP, Interconects, JESD, LIN, MIPI, PCIe, Processor Subsystems, UFS | Comments Off on Latest Buzz in Verification IP

 

Jumping the Barrier of Verifying Arm AMBA ACE Protocol Barrier Transactions

The ordering of memory transactions in Arm® AMBA® protocol is a significant requirement, i.e. the sequence of memory updates/accesses must follow a defined ordering as per the specification. Ordering is important for synchronization events by a processor with respect to retiring load/store instructions. AMBA ACE barrier transactions are used for maintaining the memory ordering across […]

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Posted in ACE, AMBA, CCI400, CHI, Interconects, Test Suites, Uncategorized | Comments Off on Jumping the Barrier of Verifying Arm AMBA ACE Protocol Barrier Transactions