Verification Central

Archive for the 'Processor Subsystems' Category

 

Get up to Speed with the Latest Arm AMBA AXI5 Features

The Arm® AMBA® 5 AXI protocol specification supports high-performance, high-frequency system designs for communication between manager and subordinate components. AMBA AXI5 protocols extend prior specification generations and add several important performance and scalability features which closely align these protocols to Arm AMBA CHI. Let’s look at some of the features of the AXI5 protocol in detail.

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Posted in AMBA, Arm, AXI

 

Synopsys Introduces the Industry’s First Verification IP for Arm AMBA 5 CHI-F

Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 CHI protocol – CHI Issue F (CHI-F). AMBA 5 CHI-F is built on top of the existing AMBA CHI Issue E (CHI-E) specification (read our blog on AMBA CHI-E here), and introduces several exciting features related to the latest Arm architecture and optimized transaction flows.

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Posted in AMBA, Arm, CHI, Data Center, Interconnects, Protocol Continuum, Test Suites

 

Utilize Advanced RPMB for Faster and More Secure UFS 4.0 Authentication

In a 5G world, fast and secure connectivity is important. The JEDEC Universal Flash Storage (UFS) version 4.0 helps to ensure this is possible in our everyday devices. As an added security element, a Replay Protected Memory Block (RPMB) is included in UFS devices as a means to store encrypted data securely, only accessible by authentication.

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Posted in Memory, MIPI, UFS

 

Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum

Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling – gathering, storing, moving, processing, and dispersing – pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.

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Posted in CXL, Data Center, Interconnects, PCIe, Protocol Continuum

 

LPDDR5X – An Extension to LPDDR5 for Future Mobile System

Emerging technologies such as Internet of Things (IoT), 5G, Automotive, Artificial Intelligence (AI), and High-Performance Computing, have given rise to potentially transformative trends demanding the need for faster memory access. 5G brings with itself the ability for faster download and upload speeds, making high-speed real-time data transfer possible. All the fancy smartphone processors have inbuilt cutting-edge features like high resolution multimedia processing, faster Machine Learning (ML) computations, Image processing capabilities and faster frame rates for all you gaming freaks. But don’t forget underlying all this, is the need for faster memory, AI/ML requires higher bandwidth to support faster processing of massive data.

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Posted in LPDDR, Memory

 

Cache Coherent Verification – New Features in AMBA®CHI

Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.

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Posted in AMBA, Arm

 

Accelerate SoC Verification, Experts available

SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.

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Posted in ACE, AMBA, CXL, Debug, Display, Ethernet, HBM, Memory, Test Suites, Verification Service

 

The wait is over – JEDEC Announces JESD79-5, DDR5 SDRAM VIP for High Performance Computing

JEDEC recently announced the ratification of JESD79-5 DDR5 SDRAM to support the standardization of next-generation memory devices, catering to demand from rapid expansion in high performance computing and data center applications. This new standard promises to deliver 2X memory bandwidth, 4X larger density dies, and much improved power efficiency (1.1V Vdd). The DDR5 DIMM will operate in dual-channel mode all on its own, with two 40-bit fully independent sub-channels on the same module.

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Posted in DDR, Memory

 

A New Generation of LPDDR

Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.

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Posted in LPDDR

 

Industry’s First VIP for AMBA CXS Enables Early Adopter Success

Synopsys offers a broad set of verification solutions for next-generation AMBA® protocols, including AMBA CXS. Synopsys also has verification automation solutions for Arm-based protocols including VC AutoTestbench for testbench generation and VC AutoPerformance for performance verification.

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Posted in AMBA, CXS, Uncategorized, UVM