NAND Flash Memory – Key Element For Your Multi-Die System Verification – Part-1
Introduction to NAND Flash Memory
Synopsys Introduces the Industry’s First Verification IPs for Arm AMBA 5 AXI-J and APB-E
Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 AXI and APB – AXI Issue J (AXI-J) and APB issue E (APB-E). These new specifications introduce several exciting features related to the latest Arm architecture and optimized transaction flows.
Using Synopsys Smart Monitors to Improve System Performance of Your Arm SoCs
Highlights
Posted in AXI, Uncategorized, ZeBu EP1
Synopsys TileLink Interconnect Verification IP for RISC-V SoCs
What is RISC-V?
Posted in Interface Subsystems, Processor Subsystems, Uncategorized
Reviewing the Latest Arm AMBA ACE5-Lite Protocol Specification Updates
In this blog we will review the newest features released as part of the Arm® AMBA® ACE5-Lite protocol, said to improve throughput and meet the low power demands of ever evolving complex multicore SoCs including cache coherency.
Get up to Speed with the Latest Arm AMBA AXI5 Features
The Arm® AMBA® 5 AXI protocol specification supports high-performance, high-frequency system designs for communication between manager and subordinate components. AMBA AXI5 protocols extend prior specification generations and add several important performance and scalability features which closely align these protocols to Arm AMBA CHI. Let’s look at some of the features of the AXI5 protocol in detail.
Synopsys Introduces the Industry’s First Verification IP for Arm AMBA 5 CHI-F
Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 CHI protocol – CHI Issue F (CHI-F). AMBA 5 CHI-F is built on top of the existing AMBA CHI Issue E (CHI-E) specification (read our blog on AMBA CHI-E here), and introduces several exciting features related to the latest Arm architecture and optimized transaction flows.
Posted in AMBA, Arm, CHI, Data Center, Interconnects, Protocol Continuum, Test Suites
Utilize Advanced RPMB for Faster and More Secure UFS 4.0 Authentication
In a 5G world, fast and secure connectivity is important. The JEDEC Universal Flash Storage (UFS) version 4.0 helps to ensure this is possible in our everyday devices. As an added security element, a Replay Protected Memory Block (RPMB) is included in UFS devices as a means to store encrypted data securely, only accessible by authentication.
Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling – gathering, storing, moving, processing, and dispersing – pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.
Posted in CXL, Data Center, Interconnects, PCIe, Protocol Continuum
