Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to use the well-established PCIe infrastructure to carry coherency packets across the link with little modification. CCIX specification is compatible with PCIe base specification 4.0. PCIe implementation is extended to implement a CCIX transaction layer, responsible for carrying the coherency messages.
DSC has enabled the use of high resolution displays in televisions, PC monitors, mobiles, and automotive infotainment systems. It provides a high quality, low latency algorithm to resolve the bottleneck of high bandwidth requirements needed to support the high resolution.
We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance analyzer and protocol debug. In case you missed the latest buzz on Verification IP, you can read it here.
The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has evolved along with the memory technologies, and next generation DFI 5.0 is here to ensure higher performance in the systems using DDR5/LPDDR5. In this blog, we will discuss the new features of DFI 5.0 specification.
The HDMI forum officially released HDMI 2.1 in November, 2017. Gamers around the world saw a new ray of hope in the new features announced in the latest specification – “Enhanced refresh rate features ensure an added level of smooth and seamless motion and transitions for gaming, movies and video” (Ref: HDMI Forum releases v2.1 of the HDMI specification). These features include Variable Refresh Rate (VRR), Quick Mode Switching (QMS), and Quick Frame Transport (QMT).
Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, which are insufficient for productive debugging. Debugging SoC and block level issues using log files is tedious and time consuming. Design problems that appear in the later phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk.
High speed memory interface is a critical component to support high speed data in applications like personal computers, mobile phones, and digital cameras. These applications require a high capacity and high performance NAND flash memory, and Toggle2NAND is one of the most suitable NAND interfaces.
With the arrival of HDMI 2.1 comes an array of remarkable features including the capability to support up to 10K resolutions at 120Hz. Such high resolutions are supported for a wider range of display applications such as externally connected displays (i.e. PC monitors and televisions), embedded display interfaces within mobile systems, and automotive infotainment systems. But with higher resolutions comes the requirement for higher bandwidth.
Higher performance at lower power is the most critical requirement of SoC designs, specifically those targeted towards mobile and consumer electronics applications. VESA (Video Electronics Standards Association), the technical standards organization for computer display standards, came up with a new power saving feature called PSR (Panel Self Refresh) in eDP 1.3. It is also available as an optional feature in DisplayPort. PSR helps to extend battery life in mobile phones, notebooks, and tablets, and is quickly being adopted in high-end designs.
In today’s world of smartphones and tablets, high speed data at low power consumption is becoming increasingly important. MIPI M-PHY supports multiple applications with high data bandwidth and low power consumption which makes it a popular specification for mobile devices. Applications like JEDEC UFS 3.0 and MIPI UniPro 1.8 now support MIPI M-PHY 4.1 which provides high speed data at a rate of nearly 11Gbps (HS_G4). To learn more about latest UFS and UniPro specifications read our previous blog “High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0”. Data at such a high speed can lead to inter-symbol-interference (ISI). M-PHY provides a safety measure to prevent the loss of data at HS_G4. In this blog, we are going to talk about the ‘ADAPT’ feature and its advantages which were introduced in M-PHY 4.0.