It’s a longstanding cliché, but it is true that verification is a marathon. An integrated verification platform accompanied by a systematic verification methodology are the building blocks to manage the verification complexity of modern system-on-chip (SoC) designs. High performance simulation environment is the foundation however it is not enough to reach to the verification closure that requires regressing hardware in conjunction to real application scenarios and software.
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.
We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
MIPI CSI-2 v3.0 is here! – The industry’s First Comprehensive Solution for 5G, Imaging, Surveillance and Automotive
Smartphones have become a one-man army by incorporating fancy features like biometric authentication, telemedicine, heartrate monitoring. With increasing market demands and requirements for higher image resolutions, MIPI CSI-2 (Camera Serial Interface) has evolved tenfold from where it first started. MIPI CSI-2 v2.0 is designed for use in smartphones, Internet of Things (IoT) devices, wearables, medical devices, augmented and virtual reality. MIPI Board recently adopted MIPI CSI-2 Specification v3.0 and approved associated CTS documents, refer https://members.mipi.org/wg/All-members/document/download/79549.
Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
As Data Center and Artificial Intelligence applications take center stage , last few years have seen the advent of various high bandwidth interconnect technologies. Compute Express Link (CXL), is an aspiring new interconnect technology for high bandwidth devices such as accelerators with memory, high density compute cards, and GPU comprised accelerators. The specification is defined by CXL Consortium https://www.computeexpresslink.org/. Synopsys has developed a comprehensive CXL verification subsystem, being already used by Early Adopters planning to release their first CXL applications. CXL verification subsystem leverages industry popular Synopsys PCI Express Verification IP. Synopsys recently introduced Industry’s first CXL IP solution. For more details refer Synopsys Delivers Industry’s First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs.
Servers are the core of today’s computational world, processing and storing data on multi-user platforms. Server performance depends on latency and capacity of its memory and storage. In general, DDR-DIMMs (Double Data Rate Dual In-line Memory Modules) are used as server memory, whereas SSDs/HDDs are used as storage in server. Whenever a service request is made to the server, it may require both data processing and storage. In order to execute this service, the processor accesses DDR-DIMMs and SSDs/HDDs. In addition, SSDs/HDDs can be accessed in case of power loss, storing data using backup power sources so data can be retrieved once power is available again.
USB4 is the next generation of the Universal Serial Bus and a major update to the interface in speed and functionality. USB4 has incorporated Thunderbolt 3 capabilities, which extends support of USB interface to existing PCIE, and DisplayPort over the same USB Type-C connector. USB4 doubles the maximum overall throughput from 20Gbps to 40Gbps enabling optimized HD video and data transfer simultaneously. USB4 enables many applications using USB Type-C, which already supports power delivery, USB 3.2, USB 2.0 and other alternative protocols.