VIP Central

Archive for the 'MIPI' Category

 

MIPI I3C: A unified sensor interface

Sensors are everywhere surrounding us at home, office, cars, industry and everything else we are using today. It all started with the thermostat and first motion sensor used for an alarm system invented somewhere in 1950s. Over the period of time, rapid increase of sensors used across various applications created significant challenges, there was a need of sophistication in terms of size, electronics, packaging and integration of practically every kind of sensor one can think of. A modern sensor works the same way similar to the sensor decades ago, but is now smaller, better and much more reliable.

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Posted in I3C, MIPI, Uncategorized |

 

MIPI DevCon 2016: SoundWire VIP

MIPI DevCon 2016 was successfully held at Mountain View, California on 14-15th Sep, 2016. Synopsys MIPI protocol experts were there demonstrating our MIPI design and verification solutions for wide spectrum of markets ranging from IoT, to mobile, automotive, and consumer. During the conference Synopsys had several presentations.  One of the papers presented by Synopsys was based on a customer case study that provide an overview and successful adoption of the MIPI SoundWire VIP and Test Suites to achieve comprehensive verification and coverage closure on their latest MIPI design.

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Posted in Audio, Automotive, C-PHY, Camera, CSI, D-PHY, events, I2S, I3C, Interface Subsystems, MIPI, Mobile SoC, MPHY, SlimBus, Soundwire, Test Suites, UFS, Unipro |

 

UFS – Faster and Secured Flash Storage

In today’s connected world of smart devices, we want to access our data faster and at the same time we want it to be secured and protected from intruders. Flash memories are not only faster but secured and reliable also in its avatar as UFS – Universal Flash Storage. This blog provides an insight into various security modes of UFS devices and how to access them. It also points out how encryption is used to secure the data further.

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Posted in Flash, Memory, MIPI, UFS, Unipro |

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |

 

MIPI SoundWire: Higher Bandwidth Through Bulk Register Access

MIPI SoundWire provides an optional mechanism for transporting register operations at higher bandwidth than mandatory command mechanism.  Bulk Register Access (BRA) protocol is a particular format of data transport to achieve the higher bandwidth.  While normal commands can only be driven at the rate of one command per frame, Bulk Register Access provides the option to read/write as many as 511 registers in one frame.  So a clock frequency of 5MHz and frame size of 256*16(4096 BitSlots or 2048 clock periods) will increase the effective rate of data transfer to approximately 1.2 MBps. MIPI SoundWire supports a frequency of up to 12 MHz, so the bandwidth can be even higher. In this blog I’ll focus on what a Bulk Register Access payload stream looks like and how it can be used to achieve higher bandwidth. BRA Payload Stream Since BRA is in no way related to actual audio transport we have the freedom to choose any values of word length and sample interval as per our needs. However, there are some restrictions as our aim is to transport a minimum of 11 bytes even in the worst case scenario (with 11 bytes we are only accessing 1 byte which is defeating the whole purpose of BRA, a normal command in this case would be more efficient). To use as many bits available in a frame for transporting data, sample word length can be set equal to hwidth and sample interval equal to number of columns. HStop can be set to max column and HStart to column 0 or 1 when lane 0 is being used.  Hence the specification recommends that Port 0 should support all values of word length from 1 to 16 as it provides the most efficient packing of data.

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Posted in MIPI, Soundwire, Uncategorized |

 

MIPI D-PHY Revolutionizing Today’s Smartphone Market

We are capturing our memories in high-definition with the latest multi-megapixel cameras and playing back with the high resolution displays. This has led to a tremendous increase in data transfer and bandwidth requirements between peripherals and application processor in a mobile SoC. It’s challenging to support advanced multimedia features in the mobile phones by integrating megapixel cameras and superior resolution displays at a reduced cost and power consumption.

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Posted in Camera, CSI, D-PHY, Display, DSI, MIPI, Uncategorized |

 

MIPI UniPro Stack Based Design and Verification

Mobile phone market is very competitive and time to market is very critical for mobile system designs. It becomes important that the IP design and verification cycle is continuously optimized. MIPI UniPro is a layered protocol for interconnecting devices within a mobile system and allowing them to exchange information at high-data rates. JEDEC UFS and MIPI CSI-3 are the typical applications defined on top of UniPro stack. UniPro specification defines a set of standard signaling at application and physical layers that allows the development and verification of individual IP blocks in parallel. In this blog, I would describe various verification topologies possible in a UniPro design and stack based architecture of Synopsys UniPro VIP.

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Posted in MIPI, Mobile SoC, Uncategorized, Unipro |

 

Celebrating the Holiday Season with VIPs

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Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB |

 

Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach

MIPI Alliance’s CSI-2 (Camera Serial Interface) has achieved widespread adoption in the smartphone industry for its ease-of-use and ability to support a broad range of imaging solutions. MIPI CSI-2 v1.3, which was announced in February 2015, also offers users the opportunity to operate CSI-2 on either of two physical layer specifications: MIPI D-PHY, which CSI-2 has used traditionally, as well as MIPI C-PHY, a new PHY that MIPI first released in September 2014. Products may implement CSI-2 solutions using either or both PHYs in the same design. MIPI CSI-2 v1.3 with C-PHY provides performance gains and increased bandwidth delivery for realizing higher resolution, better color depth, and higher frame rates on image sensors while providing pin compatibility with MIPI D-PHY.

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Posted in C-PHY, Camera, CSI, D-PHY, MIPI |

 

MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges

MIPI UniPro is a recent addition to mobile chip-to-chip interconnect technology. It’s got many useful features to meet the requirements of mobile applications. That’s perhaps why Google’s Project Ara has selected MIPI UniPro and MIPI M-PHY as its backbone interconnects.

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Posted in Methodology, MIPI, Mobile SoC, MPHY, Unipro |