SoC being designed today are getting complex day by day and verification complexity increases exponentially not only due to the complexity of design but also due to the complexity of protocols. Emerging new protocols make it further difficult due to steep learning curve. Writing test cases to cover the entire protocol becomes 3-4 man year job for complex protocols like USB, PCIe, and Ethernet etc. Synopsys provides System Verilog/UVM source code test suites to verify complex protocols. Source code is provided and tests can be extended, and customized easily. You can save the efforts and time by using Synopsys test suites to jump start verification and achieve accelerated coverage closure. In this blog, we will give an overview of the USB test suite focusing on ease of integration and use.
The Universal Serial Bus (USB) had its humble beginnings in the mid-1990s to standardize the connection of computer peripherals to PCs, both to communicate and to supply electric power. Today, it has become commonplace on a variety of devices and appliances, including Smartphones, Smart TVs, Automobiles and video game consoles. USB has effectively replaced a variety of earlier interfaces, such as serial and parallel ports with speeds up to 10GB/s (with USB 3.1), as well as separate power chargers for portable devices.
Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB
Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs.
Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.
At DVCon 2015, a couple of our key customers shared their viewpoints on how they manage growing verification complexity. This video begins with Michael Sanie highlighting the Synopsys Verification Continuum, and several key technologies that currently address the industry’s need to “Shift-Left” for faster time-to-market. Later, Amol Bhinge of Freescale and Prashanth Gurunath of Xilinx share how their leading SoC design teams have achieved success by collaborating with Synopsys.
In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively?
In this blog, I describe the necessary steps one has to take while writing a sequence to make sure it can be reusable. Personally, I feel writing sequences is the most challenging part in verifying any IP. Careful planning is required to write sequences without which we end up writing one sequence for every scenario from scratch. This makes sequences hard to maintain and debug.
As you may know, USB3.0 has a state machine called LTSSM (Link training and status state machine) which is responsible for
In this talk, Synopsys R&D Director Bernie DeLay describes advanced methods for protocol-aware debug and how to use advanced debug techniques like protocol abstraction in a unified debug environment to find the root cause of errors for the most complex of bus and interface protocols: http://youtu.be/FFO5vtH6QDI