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Archive for the 'USB' Category

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event. Synopsys hosted the annual “SoC Leaders Verify with Synopsys” Verification luncheon.  The luncheon featured industry experts and executives from Cavium, NXP, Qualcomm and Samsung, and drove our main messages of collaboration, with […]

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM | Comments Off on Verification Highlights from DAC 2016

 

Integrate USB Test Suite Quickly to Jump Start Verification

SoC being designed today are getting complex day by day and verification complexity increases exponentially not only due to the complexity of design but also due to the complexity of protocols. Emerging new protocols make it further difficult due to steep learning curve. Writing test cases to cover the entire protocol becomes 3-4 man year […]

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Posted in Test Suites, USB | Comments Off on Integrate USB Test Suite Quickly to Jump Start Verification

 

USB Power Delivery Days: Meeting Verification Challenges

The Universal Serial Bus (USB) had its humble beginnings in the mid-1990s to standardize the connection of computer peripherals to PCs, both to communicate and to supply electric power. Today, it has become commonplace on a variety of devices and appliances, including Smartphones, Smart TVs, Automobiles and video game consoles. USB has effectively replaced a […]

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Posted in Automotive, Mobile SoC, USB | Comments Off on USB Power Delivery Days: Meeting Verification Challenges

 

Celebrating the Holiday Season with VIPs

The Holiday Season is upon us. As you stand in lines, wait for packages to arrive, keep in mind that Synopsys continues to provide you the highest level of service: support, available protocols and deployment of new titles that you, our current and future VIP customer, deserve. It has been a wonderful year — many […]

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Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB | Comments Off on Celebrating the Holiday Season with VIPs

 

Protocol Debug for Complex SoCs

Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs. You can learn more about our VIPs at Verification IP Overview.

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Posted in AMBA, DDR, Debug, Methodology, PCIe, Processor Subsystems, Storage, USB | Comments Off on Protocol Debug for Complex SoCs

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans. You can learn more […]

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM | Comments Off on Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

 

Freescale and Xilinx Engineers: Managing SoC Verification Complexity

At DVCon 2015, a couple of our key customers shared their viewpoints on how they manage growing verification complexity. This video begins with Michael Sanie highlighting the Synopsys Verification Continuum, and several key technologies that currently address the industry’s need to “Shift-Left” for faster time-to-market. Later, Amol Bhinge of Freescale and Prashanth Gurunath of Xilinx […]

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Posted in AMBA, Audio, Camera, DDR, Debug, DesignWare, Display, HDMI, Interface Subsystems, LPDDR, Methodology, MIPI, Mobile SoC, PCIe, SystemVerilog, Test Suites, USB, UVM | Comments Off on Freescale and Xilinx Engineers: Managing SoC Verification Complexity

 

Virtual Sequences in UVM: Why, How?

In my previous blog post, I discussed guidelines to create reusable sequences. Continuing on this thread, here I am going to talk about virtual sequences and the virtual sequencer. Common questions I hear from users include: why do we need a virtual sequence? How can we use it effectively? Here’s where you can find more […]

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Posted in AMBA, Audio, Debug, Interface Subsystems, Methodology, MIPI, Mobile SoC, SystemVerilog, USB, UVM | Comments Off on Virtual Sequences in UVM: Why, How?

 

Reusable Sequences in UVM

In this blog, I describe the necessary steps one has to take while writing a sequence to make sure it can be reusable. Personally, I feel writing sequences is the most challenging part in verifying any IP. Careful planning is required to write sequences without which we end up writing one sequence for every scenario […]

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Posted in Debug, Methodology, SystemVerilog, USB, UVM | Comments Off on Reusable Sequences in UVM

 

Ins and outs of SS Link Training in USB3.0

As you may know, USB3.0 has a state machine called LTSSM (Link training and status state machine) which is responsible for Initialization and link training Power management transitions Link error recovery and other connectivity issues. Here’s where you can find more information on our Verification IP. LTSSM has 12 high level states as shown below. In […]

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Posted in Methodology, SystemVerilog, USB | Comments Off on Ins and outs of SS Link Training in USB3.0