The latest buzzword in the world of TVs and smartphones is High Dynamic Range (HDR). Many of us might already know that an HDR TV improves the viewing experience by offering better picture quality, just like people who use the latest smartphones know that turning on the HDR mode in the camera helps in capturing more lively pictures. In November 2017, the HDMI forum officially released HDMI 2.1 adding more to our joy, by offering the new and improved HDR. The announcement goes on to say “Dynamic HDR support ensures every moment of a video is displayed at its ideal values for depth, detail, brightness, contrast and wider color gamuts—on a scene-by-scene or even a frame-by-frame basis”. Before we explore HDR and Dynamic HDR in detail, let’s first understand how Standard Dynamic Range (SDR) works.
We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized |
We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance analyzer and protocol debug. In case you missed the latest buzz on Verification IP, you can read it here.
In today’s world of smartphones and tablets, high speed data at low power consumption is becoming increasingly important. MIPI M-PHY supports multiple applications with high data bandwidth and low power consumption which makes it a popular specification for mobile devices. Applications like JEDEC UFS 3.0 and MIPI UniPro 1.8 now support MIPI M-PHY 4.1 which provides high speed data at a rate of nearly 11Gbps (HS_G4). To learn more about latest UFS and UniPro specifications read our previous blog “High Speed Memory in Smart Phones: MIPI UniPro v1.8 for JEDEC UFS v3.0”. Data at such a high speed can lead to inter-symbol-interference (ISI). M-PHY provides a safety measure to prevent the loss of data at HS_G4. In this blog, we are going to talk about the ‘ADAPT’ feature and its advantages which were introduced in M-PHY 4.0.
One could argue that camera has been the most fascinating feature of smart phones in recent years. The latest camera phones are capable of not only capturing minute details with multi-mega pixels, but also sensing the presence of various objects. MIPI CSI-2 (Camera Serial Interface) is a high-bandwidth interface between a camera and a host processor. MIPI CSI-2 v1.1 got introduced in 2011 to fulfill the basic camera requirements of mobile applications. Next generation MIPI CSI-2 v2.0 and v2.1 have evolved to meet the requirements of emerging imaging and vision applications like wearables, IoT, drones, automotive, and security surveillance beyond smart phones. Read our previous blog to know more about MIPI CSI-2 v2.0: Emerging Applications in IoT, Drones and Automotive. The new features of MIPI CSI-2 v2.1 are outlined below:
New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency. Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.” Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM |
This year, MIPI DevCon was held in Bangalore, India and Hsinchu City, Taiwan in October. Synopsys MIPI protocol experts hosted several demos at each conference showcasing implementation experiences, use cases and application examples within mobile, automotive, IoT and mixed reality applications.
Higher storage performance at a lower cost can create a bottleneck in the design of storage devices. In order to achieve higher performance, devices must use on chip DRAM, which adds to the overall cost. This is where Unified Memory Extension (UME), a JEDEC specification, comes into the picture. It is defined as extension to the JEDEC UFS (Universal Flash Storage) specification. JEDEC UFS device uses NAND flash technology for data storage. Unified Memory (UM) allows users to use part of the host memory as the device’s internal memory. Since the host memory is already available in large capacities, this mechanism provides a much bigger space for the device to use as a Write Buffer (WB) cache or to store information such as Logical to Physical (L2P) address translation tables. The UM area is physically located on the host side but ultimately belongs to the device, thereby replacing the device-integrated RAM, and reducing overall cost. Large space availability means the device can store larger amounts of WB of L2P table information resulting in higher storage performance.
MIPI Camera Serial Interface (CSI-2) is widely used as a camera interface in the mobile industry. MIPI Alliance is constantly working towards providing a solution to cater the increasing demand for higher-bandwidth and high-definition video like 1080p, 4K, and 8K. The MIPI Working Group released CSI-2 v2.0 to target emerging imaging and vision applications. It has extended the usages of CSI-2 to IoT, wearable devices, drones, Virtual Reality (VR) and Augmented Reality (AR), and automotive systems.