It’s a longstanding cliché, but it is true that verification is a marathon. An integrated verification platform accompanied by a systematic verification methodology are the building blocks to manage the verification complexity of modern system-on-chip (SoC) designs. High performance simulation environment is the foundation however it is not enough to reach to the verification closure that requires regressing hardware in conjunction to real application scenarios and software.
We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized
This year, MIPI DevCon was held in Bangalore, India and Hsinchu City, Taiwan in October. Synopsys MIPI protocol experts hosted several demos at each conference showcasing implementation experiences, use cases and application examples within mobile, automotive, IoT and mixed reality applications.
MIPI DevCon 2016 was successfully held at Mountain View, California on 14-15th Sep, 2016. Synopsys MIPI protocol experts were there demonstrating our MIPI design and verification solutions for wide spectrum of markets ranging from IoT, to mobile, automotive, and consumer. During the conference Synopsys had several presentations. One of the papers presented by Synopsys was based on a customer case study that provide an overview and successful adoption of the MIPI SoundWire VIP and Test Suites to achieve comprehensive verification and coverage closure on their latest MIPI design.
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM
The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.
Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM
MIPI SoundWire provides an optional mechanism for transporting register operations at higher bandwidth than mandatory command mechanism. Bulk Register Access (BRA) protocol is a particular format of data transport to achieve the higher bandwidth. While normal commands can only be driven at the rate of one command per frame, Bulk Register Access provides the option to read/write as many as 511 registers in one frame. So a clock frequency of 5MHz and frame size of 256*16(4096 BitSlots or 2048 clock periods) will increase the effective rate of data transfer to approximately 1.2 MBps. MIPI SoundWire supports a frequency of up to 12 MHz, so the bandwidth can be even higher. In this blog I’ll focus on what a Bulk Register Access payload stream looks like and how it can be used to achieve higher bandwidth. BRA Payload Stream Since BRA is in no way related to actual audio transport we have the freedom to choose any values of word length and sample interval as per our needs. However, there are some restrictions as our aim is to transport a minimum of 11 bytes even in the worst case scenario (with 11 bytes we are only accessing 1 byte which is defeating the whole purpose of BRA, a normal command in this case would be more efficient). To use as many bits available in a frame for transporting data, sample word length can be set equal to hwidth and sample interval equal to number of columns. HStop can be set to max column and HStart to column 0 or 1 when lane 0 is being used. Hence the specification recommends that Port 0 should support all values of word length from 1 to 16 as it provides the most efficient packing of data.
Here, we describe how easy it is to integrate and validate a SoundWire design using Synopsys SoundWire VIP Test Suite.
It is estimated that every smartphone now uses some aspect of the MIPI standards. Last year, one billion phones, and about 6 to 7 billion phone ICs, included a MIPI interface of some sort. MIPI interfaces, especially for cameras and displays, have spread beyond the mobile world into other markets, such as automotive, industrial, medical, the IoT and the digital home/office.
In MIPI Soundwire: Digital Audio Simplified, we mentioned that digital audio formats, including Pulse Code Modulation (PCM) and Pulse Density Modulation (PDM), are target applications for MIPI Soundwire. Later, we discussed Digital Audio Streams and Channels. Here, we will talk about the merits MIPI Soundwire protocol has over other available digital audio interfaces.