Verification Central

Archive for the 'Interface Subsystems' Category

 

Keeping Up with UCIe 1.1 Verification Using Synopsys VIP for UCIe

Ever since UCIe™ (Universal Chiplet Interconnect Express™) consortium was formed and version 1.0 of the UCIe specification was released, the chiplet/die-to-die ecosystem has been frenzied. IP architects and developers have their task cut-out for them – to come up with a robust design and implementation that benefits from the heterogenous system without compromising their power, performance, and area (PPA) goals. System architects and designers are busy putting the technology in their next generation SoCs. Verification teams are running against time to create test and coverage plans based on the integrated logic before they receive disintegrated chip RTL.

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Posted in 5G, CXL, Data Center, Interface Subsystems, PCIe

 

Synopsys TileLink Interconnect Verification IP for RISC-V SoCs

What is RISC-V?

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Posted in Interface Subsystems, Processor Subsystems, Uncategorized

 

Addressing the Verification Challenges of Panel Self Refresh in eDP

What is eDP (Embedded Display Port)?

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Posted in Display, DisplayPort

 

Achieve Functional Safety for Automotive and Digital Ecosystems using MIPI CSE

Today, the automotive industry is experiencing an advanced evolution which demands need for an ever-increasing bit-depths, frame rates, camera and display resolutions, and most significantly functional safety. To address these challenges and to support future architectures, the MIPI Alliance developed MIPI Automotive SerDes Solutions (MASS)  which is an end-to-end framework for connecting sensors, cameras, displays and many other industry standardized protocols with functional safety and security. In this blog we will review the features and nuances of MIPI CSE™ (Camera Service Extension) one of the key components in the MASS connectivity framework, and explain how Synopsys Verification IP (VIP) for MIPI solutions provide a comprehensive set of methodology, verification and productivity features to support these protocols.

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Posted in Automotive, Camera, CSI, IoT, MIPI

 

Utilize Advanced RPMB for Faster and More Secure UFS 4.0 Authentication

In a 5G world, fast and secure connectivity is important. The JEDEC Universal Flash Storage (UFS) version 4.0 helps to ensure this is possible in our everyday devices. As an added security element, a Replay Protected Memory Block (RPMB) is included in UFS devices as a means to store encrypted data securely, only accessible by authentication.

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Posted in Memory, MIPI, UFS

 

Say Goodbye to blank screens with HDMI’s Quick Media Switching

 

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Posted in AI, Data Center, Display, HDMI, Uncategorized

 

Attention Gamers! HDMI 2.1a Introduces Source Based Tone Mapping (SBTM)

HDMI (High-Definition Multimedia Interface) is the most popular medium for transporting both audio and video information between two digital devices. In the past two decades, HDMI technology has evolved from HDMI 1.0 to HDMI 2.0. In 2017 HDMI 2.1 introduced enhanced gaming and media features such as Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM) to eliminate lag, stutter, and tearing, adding smoothness to the gaming and video experience. Recently the HDMI Forum has announced a new version, HDMI2.1a, that brings a standout gamer-friendly feature, Source-Based Tone Mapping (SBTM).

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Posted in Display, HDMI, Protocol Continuum

 

Reduced Blanking: The Way to Low Power, High Resolution Displays

With the release of HDMI 2.1, higher video resolutions and refresh rates including 8K@60Hz and 4K@120Hz are a reality. In a previous blog, 10K Resolution at 120Hz Display: A Reality Today with DSC 1.2 in HDMI 2.1, we explained how HDMI 2.1 can support resolutions and refresh rates of the order 4K@240Hz, 8K@120Hz and 10K@120Hz with display stream compression (DSC). With increased resolution you get finer details and with higher refresh rate the moving content feels smoother. But it also means more pixel information and thus higher data transmission rate, higher bandwidth, and higher power consumption. What if there is a way to reduce the transmission rate while keeping the resolution and refresh rate intact? The answer lies in the reduced blanking feature in which the blanking region of a frame is reduced significantly.

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Posted in Display, HDMI, MIPI

 

Accelerate SoC Verification, Experts available

SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.

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Posted in ACE, AMBA, CXL, Debug, Display, Ethernet, HBM, Memory, Test Suites, Verification Service

 

Understanding Color Space Conversions in Display

Color space is a very powerful tool that comes in handy when capturing, transmitting and reproducing color back to the human eye. Systems such as cameras, GPUs, transmission cables (HDMI/DP), and monitors use color space metrics to preserve and transform color. This technology helps map real colors to the color model’s discrete values.

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Posted in Camera, Display, DisplayPort