We recently published the VIP Newsletter for Apr 2019, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
The most awaited news of the year is officially here! USB Promoter Group has officially announced USB4 specification, which is an extensive upgrade over USB 3.2 specification. The new specification guarantees double the speed of USB 3.2 Gen 2×2, and has built in Thunderbolt™ 3 compatibility. The official specification release is expected by mid-2019.
The key features driving future memories are memory density, speed, lower operating voltage, and faster access. DDR5 supports memory density from 8Gb to 64Gb combined with a wide range of data rate from 3200 MT/s to 6400 MT/s. The operating voltage of DDR5 is further reduced from 1.2V of DDR4 to 1.1V.
High resolution 8k UHD displays for emerging technologies like connected cars, IoT, and AR/VR (Augmented/Virtual Reality) require high bandwidth to support the high-resolution transmission. MIPI DSI is the widely used display interface, but the bandwidth provided by PHY layers isn’t sufficient enough to support the high-resolution displays; therefore, a compression technique like DSC (Display Stream Compression) is required. One of our recent blog discussed about DSC 1.2 in HDMI 2.1 – High Resolution Displays for Mobile, TV, PC and Automotive Enabled by DSC 1.2 in HDMI 2.1. In this blog, we will see how DSC 1.2 enables MIPI DSI to support the high-resolution displays for emerging applications.
The latest buzzword in the world of TVs and smartphones is High Dynamic Range (HDR). Many of us might already know that an HDR TV improves the viewing experience by offering better picture quality, just like people who use the latest smartphones know that turning on the HDR mode in the camera helps in capturing more lively pictures. In November 2017, the HDMI forum officially released HDMI 2.1 adding more to our joy, by offering the new and improved HDR. The announcement goes on to say “Dynamic HDR support ensures every moment of a video is displayed at its ideal values for depth, detail, brightness, contrast and wider color gamuts—on a scene-by-scene or even a frame-by-frame basis”. Before we explore HDR and Dynamic HDR in detail, let’s first understand how Standard Dynamic Range (SDR) works.
Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.
We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.
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HDMI 2.1/2.0 bring significant improvements over previous versions in terms of speed, data integrity, and mode of data transmission. For more details on how HDMI has evolved, read our previous blog – HDMI 1.4 to 2.1: How it Became the Most Popular Display Interface.
Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to use the well-established PCIe infrastructure to carry coherency packets across the link with little modification. CCIX specification is compatible with PCIe base specification 4.0. PCIe implementation is extended to implement a CCIX transaction layer, responsible for carrying the coherency messages.
DSC has enabled the use of high resolution displays in televisions, PC monitors, mobiles, and automotive infotainment systems. It provides a high quality, low latency algorithm to resolve the bottleneck of high bandwidth requirements needed to support the high resolution.