Ever since UCIe™ (Universal Chiplet Interconnect Express™) consortium was formed and version 1.0 of the UCIe specification was released, the chiplet/die-to-die ecosystem has been frenzied. IP architects and developers have their task cut-out for them – to come up with a robust design and implementation that benefits from the heterogenous system without compromising their power, performance, and area (PPA) goals. System architects and designers are busy putting the technology in their next generation SoCs. Verification teams are running against time to create test and coverage plans based on the integrated logic before they receive disintegrated chip RTL.
Introduction to NAND Flash Memory
Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 AXI and APB – AXI Issue J (AXI-J) and APB issue E (APB-E). These new specifications introduce several exciting features related to the latest Arm architecture and optimized transaction flows.
What is RISC-V?
What is eDP (Embedded Display Port)?
Today, the automotive industry is experiencing an advanced evolution which demands need for an ever-increasing bit-depths, frame rates, camera and display resolutions, and most significantly functional safety. To address these challenges and to support future architectures, the MIPI Alliance developed MIPI Automotive SerDes Solutions (MASS) which is an end-to-end framework for connecting sensors, cameras, displays and many other industry standardized protocols with functional safety and security. In this blog we will review the features and nuances of MIPI CSE™ (Camera Service Extension) one of the key components in the MASS connectivity framework, and explain how Synopsys Verification IP (VIP) for MIPI solutions provide a comprehensive set of methodology, verification and productivity features to support these protocols.
In this blog we will review the newest features released as part of the Arm® AMBA® ACE5-Lite protocol, said to improve throughput and meet the low power demands of ever evolving complex multicore SoCs including cache coherency.
The Arm® AMBA® 5 AXI protocol specification supports high-performance, high-frequency system designs for communication between manager and subordinate components. AMBA AXI5 protocols extend prior specification generations and add several important performance and scalability features which closely align these protocols to Arm AMBA CHI. Let’s look at some of the features of the AXI5 protocol in detail.