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Archive for the 'Mobile SoC' Category

 

A New Generation of LPDDR

Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.

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Posted in LPDDR |

 

Understanding Color Space in Display

The color space is a very powerful tool that comes in handy when capturing and transmitting color back to the human eye. All systems like cameras, GPUs, transmission cables (HDMI/DP), monitors, etc. use color space metrics to preserve and transform color.  

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Posted in Display, DisplayPort |

 

Automating Testbench Creation to Accelerate Network-on-Chip Verification

Network-on-Chip (NoC) is a critical building block for many advanced and complex system-on-chips (SoCs). Having a complete verification solution to verify the functionality along with the performance (latency/bandwidth) is a must to ensure there are no functional bugs and no performance bottlenecks.

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Posted in Arm, Data Center, Debug, Mobile SoC, Uncategorized |

 

Industry’s First VIP for Arm AMBA CXS Enables Early Adopter Success

Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, now including AMBA CXS. Synopsys also has verification automation solutions for Arm based protocols including VC AutoTestbench for testbench generation and VC AutoPerformance for performance verification.

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Posted in AMBA, Arm, CXS, Uncategorized, UVM |

 

DDR5 – Off and Running

The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.

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Posted in DDR, Memory |

 

An Introduction to the CXL Device Types

Compute Express Link (CXL) is the latest specification in interconnect technology for high bandwidth devices. It provides high-speed, efficient connectivity from CPUs to other components of the high-performance computing platform.

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Posted in Interface Subsystems, Uncategorized, UVM |

 

Simplify Entertainment with HDMI 2.1 eARC

HDMI (High-Definition Multimedia Interface) has been a part of our entertainment systems for nearly two decades now. Though the look of the cable has remained the same over the years, the input has undergone many improvements since its release in 2002.

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Posted in Debug, Display, DisplayPort, Uncategorized, UVM |

 

Deciphering the New TileLink Standard

Increasing complexities of processor architectures with limited overall performance scale-up have created a demand for a domain specific architecture to ensure extensive performance scaling. – this is when RISC-V began to gain momentum. RISC-V is gathering widespread attention throughout sectors like datacenter accelerators, mobile & wireless, IoT, etc. for its extensibility. Many industry leaders are beginning to adopt RISC-V for its open source availability that reduces time-to-market and cost effectiveness while at the same time scaling up the overall performance and leaving room for innovation and automation.

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Posted in Mobile SoC, Processor Subsystems, Uncategorized |

 

The Power Of HDMI ARC

HDMI ARC, What is it and Why You Should Care?

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Posted in Display, HDMI, Uncategorized |

 

Faster closure, simulation acceleration to emulation

It’s a longstanding cliché, but it is true that verification is a marathon. An integrated verification platform accompanied by a systematic verification methodology are the building blocks to manage the verification complexity of modern system-on-chip (SoC) designs. High performance simulation environment is the foundation however it is not enough to reach to the verification closure that requires regressing hardware in conjunction to real application scenarios and software.

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Posted in Audio, Automotive, Camera, IoT, Mobile SoC, UFS, UVM |