SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.
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Posted in ACE, AMBA, CXL, Debug, Display, Ethernet, HBM, Memory, Test Suites, Verification Service
Color space is a very powerful tool that comes in handy when capturing, transmitting and reproducing color back to the human eye. Systems such as cameras, GPUs, transmission cables (HDMI/DP), and monitors use color space metrics to preserve and transform color. This technology helps map real colors to the color model’s discrete values.
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Posted in Camera, Display, DisplayPort
Lately television lovers across the world have an even better reason to be glued to the small screens, as 8K Ultra HD TVs have made their way to the market. The HDMI forums most recently released specification, v2.1, explains “higher video resolutions support a range of high resolutions and faster refresh rates including 8K60Hz and 4K120Hz for immersive viewing and smooth fast-action detail…” Most of us are familiar with the word “resolution”, but do we really know this term well?
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Posted in Camera, Display, HDMI, Uncategorized
JEDEC recently announced the ratification of JESD79-5 DDR5 SDRAM to support the standardization of next-generation memory devices, catering to demand from rapid expansion in high performance computing and data center applications. This new standard promises to deliver 2X memory bandwidth, 4X larger density dies, and much improved power efficiency (1.1V Vdd). The DDR5 DIMM will operate in dual-channel mode all on its own, with two 40-bit fully independent sub-channels on the same module.
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Posted in DDR, Memory
Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.
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Posted in LPDDR
The color space is a very powerful tool that comes in handy when capturing and transmitting color back to the human eye. All systems like cameras, GPUs, transmission cables (HDMI/DP), monitors, etc. use color space metrics to preserve and transform color.
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Posted in Display, DisplayPort
Network-on-Chip (NoC) is a critical building block for many advanced and complex system-on-chips (SoCs). Having a complete verification solution to verify the functionality along with the performance (latency/bandwidth) is a must to ensure there are no functional bugs and no performance bottlenecks.
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Posted in Arm, Data Center, Debug, Mobile SoC, Uncategorized
Synopsys offers a broad set of verification solutions for next-generation AMBA® protocols, including AMBA CXS. Synopsys also has verification automation solutions for Arm-based protocols including VC AutoTestbench for testbench generation and VC AutoPerformance for performance verification.
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Posted in AMBA, CXS, Uncategorized, UVM
The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.
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Posted in DDR, Memory
Compute Express Link (CXL) is the latest specification in interconnect technology for high bandwidth devices. It provides high-speed, efficient connectivity from CPUs to other components of the high-performance computing platform.
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Posted in CXL, Interface Subsystems, UVM
