Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
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Posted in ACE, AMBA |
Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.
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Posted in AMBA, Interconnects, Mobile SoC, Processor Subsystems, Uncategorized |
We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.
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Posted in LPDDR, Memory, Uncategorized |
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
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Posted in Debug, Memory, Uncategorized |
Smartphones have become a one-man army by incorporating fancy features like biometric authentication, telemedicine, heartrate monitoring. With increasing market demands and requirements for higher image resolutions, MIPI CSI-2 (Camera Serial Interface) has evolved tenfold from where it first started. MIPI CSI-2 v2.0 is designed for use in smartphones, Internet of Things (IoT) devices, wearables, medical devices, augmented and virtual reality. MIPI Board recently adopted MIPI CSI-2 Specification v3.0 and approved associated CTS documents, refer https://members.mipi.org/wg/All-members/document/download/79549.
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Posted in 5G, Automotive, C-PHY, Camera, CSI, MIPI, Mobile SoC, MPHY |
Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
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Posted in Memory, SystemVerilog |
As Data Center and Artificial Intelligence applications take center stage , last few years have seen the advent of various high bandwidth interconnect technologies. Compute Express Link (CXL), is an aspiring new interconnect technology for high bandwidth devices such as accelerators with memory, high density compute cards, and GPU comprised accelerators. The specification is defined by CXL Consortium https://www.computeexpresslink.org/. Synopsys has developed a comprehensive CXL verification subsystem, being already used by Early Adopters planning to release their first CXL applications. CXL verification subsystem leverages industry popular Synopsys PCI Express Verification IP. Synopsys recently introduced Industry’s first CXL IP solution. For more details refer Synopsys Delivers Industry’s First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs.
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Posted in DesignWare, Interconnects, Mobile SoC, PCIe |
Servers are the core of today’s computational world, processing and storing data on multi-user platforms. Server performance depends on latency and capacity of its memory and storage. In general, DDR-DIMMs (Double Data Rate Dual In-line Memory Modules) are used as server memory, whereas SSDs/HDDs are used as storage in server. Whenever a service request is made to the server, it may require both data processing and storage. In order to execute this service, the processor accesses DDR-DIMMs and SSDs/HDDs. In addition, SSDs/HDDs can be accessed in case of power loss, storing data using backup power sources so data can be retrieved once power is available again.
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Posted in Flash, Memory, UVM |
USB4 is the next generation of the Universal Serial Bus and a major update to the interface in speed and functionality. USB4 has incorporated Thunderbolt 3 capabilities, which extends support of USB interface to existing PCIE, and DisplayPort over the same USB Type-C connector. USB4 doubles the maximum overall throughput from 20Gbps to 40Gbps enabling optimized HD video and data transfer simultaneously. USB4 enables many applications using USB Type-C, which already supports power delivery, USB 3.2, USB 2.0 and other alternative protocols.
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Posted in DisplayPort, SystemVerilog, Test Suites, USB |
The demand for higher resolution displays is exploding across the market segments from electronics like television, monitors, laptops, and smartphones to the emerging technologies like video and vision, automotive, and AR/VR. The bandwidth requirement for displays increases multi-fold with higher resolution which has been the main driver for development of the latest DisplayPort 2.0 specification by VESA.
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Posted in Automotive, Display, DisplayPort, DSC, DSI, HDCP, HDMI, MHL, Mobile SoC |
