VIP Central

Archive for the 'UVM' Category

 

Introducing Synopsys VIP for PCIe Gen4

Here, Paul Graykowski, Corporate Applications Engineer at Synopsys, describes what our Verification IP for PCIe Gen4 can do for you.

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Posted in Data Center, Debug, Methodology, PCIe, SystemVerilog, UVM |

 

Increase Productivity with Synopsys Memory VIP

In this video, you will learn how to increase productivity with Synopsys Memory VIP.

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Posted in DDR, Debug, DFI, eMMC, Flash, HBM, HMC, LPDDR, Memory, Methodology, ONFi, UFS, UVM |

 

SoC Leaders Verify with Synopsys: DAC 2015 Verification Luncheon

Featuring speakers from Altera, AMD, ARM, Cavium and Freescale During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.

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Posted in Debug, Methodology, Mobile SoC, Processor Subsystems, Success Stories, SystemVerilog, UVM |

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM |

 

DAC 2015, San Francisco: Must-See Verification Sessions

It’s going to be an exciting week for  designers and verification engineers at the Design Automation Conference in San Francisco this week. Here’s a list of activities we recommend:

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Posted in Methodology, SystemVerilog, UVM |

 

Performance Advantages of Synopsys VIP

In this video, you will learn how several users are benefiting from the performance advantage of using Synopsys VIP  http://bit.ly/1Kau83g

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Posted in Debug, SystemVerilog, Test Suites, UVM |

 

AMBA System Monitor, Scoreboarding and Beyond

In my previous blog post, How do you Verify the AMBA System Level Environment? we discussed how to enable SOC verification engineers to create highly configurable AMBA fabric.

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Posted in AMBA, Methodology, SystemVerilog, UVM |

 

PCIe: Monitors and Test Suites

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP Monitor and Test Suites http://bit.ly/1DHIdyQ

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Posted in Debug, PCIe, SystemVerilog, Test Suites, UVM |

 

PCIe: Accelerating Debug

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the debug process:

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Posted in Debug, PCIe, SystemVerilog, UVM |

 

PCIe VIP: Accelerating Verification

In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the verification process: http://bit.ly/1CWit0q

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Posted in Methodology, PCIe, SystemVerilog, UVM |