Verification Central

Archive for the 'UVM' Category

 

NVMe VIP Architecture: Host Features

In my last post, I covered a basic NVMe VIP test-case including some basic setup, sending a command and receiving a completion. Here, we’ll look at a few more NVMe commands, touching on some of the features and capabilities of the VIP.

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Posted in Methodology, NVMe, PCIe, UVM

 

MIPI I3C VIP Accelerates Scalable Sensor Interfaces on Mobile Devices

As sensors continue to get smaller, more powerful and cheaper, smartphones and other mobile devices incorporate over ten sensors to create self-aware devices. For instance, most recent models of Apple and Samsung handheld devices use several sensors to perform some of their coolest interface tricks: proximity sensor, accelerometer (motion sensor), ambient light sensor, moisture sensor, gyroscope, thermometer and magnetometer (compass). These sensors enable key capabilities for users including location services, health apps, fingerprint scanning and sophisticated gaming while optimizing power usage and WiFi access.  

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Posted in Debug, I3C, Mobile SoC, SystemVerilog, UVM

 

First Ethernet 400G VIP to Enable Next-Gen Networking and Communications SoCs

On Monday, Synopsys announced the availability of the industry’s first verification IP (VIP) and source code test suite to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard (400GbE). To understand how it will enable next generation networking and communication systems, we take a look at the evolution of the Ethernet.

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Posted in Data Center, Ethernet, Methodology, SystemVerilog, Test Suites, UVM

 

PCIe Gen4 – VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites

Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging.  This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure.

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Posted in Debug, Methodology, PCIe, SystemVerilog, Test Suites, UVM

 

Synopsys NVMe VIP Architecture: The Host Protocol Layers

Our previous post on NVMe was an overview of the NVMe protocol. We will now start looking closer at the VIP-proper, looking initially at the NVMe Host Protocol layers. This will provide an introductory overview of sending commands to the NVMe Controller.

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Posted in Methodology, NVMe, PCIe, UVM

 

Introducing Synopsys VIP for PCIe Gen4

Here, Paul Graykowski, Corporate Applications Engineer at Synopsys, describes what our Verification IP for PCIe Gen4 can do for you.

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Posted in Data Center, Debug, Methodology, PCIe, SystemVerilog, UVM

 

Increase Productivity with Synopsys Memory VIP

In this video, you will learn how to increase productivity with Synopsys Memory VIP.

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Posted in DDR, Debug, DFI, eMMC, Flash, HBM, HMC, LPDDR, Memory, Methodology, ONFi, UFS, UVM

 

SoC Leaders Verify with Synopsys: DAC 2015 Verification Luncheon

Featuring speakers from Altera, AMD, ARM, Cavium and Freescale During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.

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Posted in Debug, Methodology, Mobile SoC, Processor Subsystems, Success Stories, SystemVerilog, UVM

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM

 

DAC 2015, San Francisco: Must-See Verification Sessions

It’s going to be an exciting week for  designers and verification engineers at the Design Automation Conference in San Francisco this week. Here’s a list of activities we recommend:

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Posted in Methodology, SystemVerilog, UVM