In this video, you will learn how to increase productivity with Synopsys Memory VIP.
Featuring speakers from Altera, AMD, ARM, Cavium and Freescale During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.
Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.
It’s going to be an exciting week for designers and verification engineers at the Design Automation Conference in San Francisco this week. Here’s a list of activities we recommend:
In this video, you will learn how several users are benefiting from the performance advantage of using Synopsys VIP http://bit.ly/1Kau83g
In my previous blog post, How do you Verify the AMBA System Level Environment? we discussed how to enable SOC verification engineers to create highly configurable AMBA fabric.
In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP Monitor and Test Suites http://bit.ly/1DHIdyQ
In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the debug process:
In this video, Paul Graykowski of Synopsys gives an overview of the PCI Express VIP’s capabilities that will support your efforts to accelerate the verification process: http://bit.ly/1CWit0q
At DVCon 2015, a couple of our key customers shared their viewpoints on how they manage growing verification complexity. This video begins with Michael Sanie highlighting the Synopsys Verification Continuum, and several key technologies that currently address the industry’s need to “Shift-Left” for faster time-to-market. Later, Amol Bhinge of Freescale and Prashanth Gurunath of Xilinx share how their leading SoC design teams have achieved success by collaborating with Synopsys.