Servers are the core of today’s computational world, processing and storing data on multi-user platforms. Server performance depends on latency and capacity of its memory and storage. In general, DDR-DIMMs (Double Data Rate Dual In-line Memory Modules) are used as server memory, whereas SSDs/HDDs are used as storage in server. Whenever a service request is made to the server, it may require both data processing and storage. In order to execute this service, the processor accesses DDR-DIMMs and SSDs/HDDs. In addition, SSDs/HDDs can be accessed in case of power loss, storing data using backup power sources so data can be retrieved once power is available again.
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM |
Arm TechCon 2017 took place at Santa Clara on 24-26th Oct, 2017. This year, Synopsys’ Arm® AMBA® protocol experts were on hand to demonstrate our verification automation solutions for Arm AMBA Coherent Interconnects. Synopsys Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances. Our experts also introduced our AMBA AutoPerformance solution to generate AMBA(CHI/ACE/AXI) interconnect performance verification stimulus. The AutoPerformance solution, based on Arm traffic profile specification, enables user to define traffic profiles for measurement of performance metrics like throughput, latency etc., and the stimulus is driven by VIP for AMBA (CHI/ACE/AXI).
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |
The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.
Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM |
In my last post, I covered a basic NVMe VIP test-case including some basic setup, sending a command and receiving a completion. Here, we’ll look at a few more NVMe commands, touching on some of the features and capabilities of the VIP.
As sensors continue to get smaller, more powerful and cheaper, smartphones and other mobile devices incorporate over ten sensors to create self-aware devices. For instance, most recent models of Apple and Samsung handheld devices use several sensors to perform some of their coolest interface tricks: proximity sensor, accelerometer (motion sensor), ambient light sensor, moisture sensor, gyroscope, thermometer and magnetometer (compass). These sensors enable key capabilities for users including location services, health apps, fingerprint scanning and sophisticated gaming while optimizing power usage and WiFi access.
On Monday, Synopsys announced the availability of the industry’s first verification IP (VIP) and source code test suite to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard (400GbE). To understand how it will enable next generation networking and communication systems, we take a look at the evolution of the Ethernet.
Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging. This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure.
Our previous post on NVMe was an overview of the NVMe protocol. We will now start looking closer at the VIP-proper, looking initially at the NVMe Host Protocol layers. This will provide an introductory overview of sending commands to the NVMe Controller.