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Latest Buzz in Verification IP

 

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Posted in ACE, AMBA, Automotive, CAN, CCI400, CHI, Data Center, Display, DisplayPort, eMMC, Ethernet AVB, FlexRay, HDCP, Interconnects, JESD, LIN, MIPI, PCIe, Processor Subsystems, UFS |

 

Is JESD204B A New Buzz Word In FPGA?

The JESD204B specification is the newer version published by JEDEC standard for data converters and logic devices. If you are working on high-speed data capture designs using an FPGA, you’ve would have heard the new buzz word, ‘JESD204B’. This newer version provides significant benefits over LVDS and CMOS interfaces, as it includes an easier layout and reduced pin-count. The JESD204B standard has a layered architecture, and is comprised of 3 layers beginning with Transport Layer at top, extending to Link Layer in middle and Physical layer at the bottom. Mirror Image is the structure at receiver side, with bottom up approach (Physical layer -> Link layer -> Transport layer). Each layer has a unique function to perform.

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JESD204B: New Alternative for High-Speed Data Acquisition up to 12.5Gbps

Can your PCB handle speed up to 12.5Gbps, surprised, right? The JESD204B standard provides bit rates up to 12.5Gbps for serial interfaces. This upgrade allows designers to use fewer transceivers on FPGA/ASIC thereby reducing the I/O count and packaging size. The new standard is being adopted rapidly in high-speed data converter applications such as wireless infrastructure transceivers, software defined radios, medical imaging systems, and radar and secure communications.

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