VIP Central

Archive for the 'JESD' Category

 

Latest Buzz in Verification IP

    We recently released the Q2 VIP newsletter containing trending topics, leading solutions, in depth technical articles, videos, webinars and product announcements from VIP and protocol experts. In case you missed the latest buzz on Verification IP, you can read it here.                         […]

Continue Reading...

Posted in ACE, AMBA, Automotive, CAN, CCI400, CHI, Data Center, Display, DisplayPort, eMMC, Ethernet AVB, FlexRay, HDCP, Interconects, JESD, LIN, MIPI, PCIe, Processor Subsystems, UFS | Comments Off on Latest Buzz in Verification IP

 

Is JESD204B A New Buzz Word In FPGA?

The JESD204B specification is the newer version published by JEDEC standard for data converters and logic devices. If you are working on high-speed data capture designs using an FPGA, you’ve would have heard the new buzz word, ‘JESD204B’. This newer version provides significant benefits over LVDS and CMOS interfaces, as it includes an easier layout […]

Continue Reading...

Posted in JESD | Comments Off on Is JESD204B A New Buzz Word In FPGA?

 

JESD204B: New Alternative for High-Speed Data Acquisition up to 12.5Gbps

Can your PCB handle speed up to 12.5Gbps, surprised, right? The JESD204B standard provides bit rates up to 12.5Gbps for serial interfaces. This upgrade allows designers to use fewer transceivers on FPGA/ASIC thereby reducing the I/O count and packaging size. The new standard is being adopted rapidly in high-speed data converter applications such as wireless […]

Continue Reading...

Posted in JESD | Comments Off on JESD204B: New Alternative for High-Speed Data Acquisition up to 12.5Gbps