VIP Central

Archive for the 'Debug' Category

 

Get Ready for IoT with Synopsys PCIe VC Verification IP Workshop

Internet of Things (IoT) is connecting billions of intelligent “things” to our fingertips. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications. Servers powering the cloud will have to scale to handle these billions of intelligent things. As a preparation to that PCIe Gen 4 has been introduced. It is capable of supporting 16 T transfers/s. Current primary market driver for the PCIe Gen4 application seems to be server storage space.

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Posted in Debug, Methodology, MIPI, MPHY, PCIe, SystemVerilog |

 

Protocol Debug for Complex SoCs

Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs.

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Posted in AMBA, DDR, Debug, Methodology, PCIe, Processor Subsystems, Storage, USB |

 

Verifying and Debugging Storage Protocols: SATA

In this video, Synopsys Applications Consultant, Vijay Akkaraju, describes the evolving  Storage ecosystem, the challenges of verifying storage protocol based system, and how Synopsys’ SATA Verification IP can support you in verifying and debugging your designs efficiently and effectively.

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Posted in Debug, SATA, Storage |

 

Webinar: Accelerating Verification Closure with PCIe Gen4 VIP

In a recent post, Paul Graykowski introduced Synopsys VIP for PCIe Gen4.

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Posted in Data Center, Debug, Methodology, PCIe |

 

Introducing Synopsys VIP for PCIe Gen4

Here, Paul Graykowski, Corporate Applications Engineer at Synopsys, describes what our Verification IP for PCIe Gen4 can do for you.

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Posted in Data Center, Debug, Methodology, PCIe, SystemVerilog, UVM |

 

Increase Productivity with Synopsys Memory VIP

In this video, you will learn how to increase productivity with Synopsys Memory VIP.

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Posted in DDR, Debug, DFI, eMMC, Flash, HBM, HMC, LPDDR, Memory, Methodology, ONFi, UFS, UVM |

 

SoC Leaders Verify with Synopsys: DAC 2015 Verification Luncheon

Featuring speakers from Altera, AMD, ARM, Cavium and Freescale During DAC 2015, Synopsys hosted a luncheon event at DAC in San Francisco, CA.

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Posted in Debug, Methodology, Mobile SoC, Processor Subsystems, Success Stories, SystemVerilog, UVM |

 

Bernie DeLay @ EDACafe on the Value of SystemVerilog, UVM-based VIP

Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.

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Posted in AMBA, DDR, Debug, DesignWare, Ethernet, HDMI, LPDDR, Memory, Methodology, PCIe, SystemVerilog, Test Suites, USB, UVM |

 

Performance Advantages of Synopsys VIP

In this video, you will learn how several users are benefiting from the performance advantage of using Synopsys VIP  http://bit.ly/1Kau83g

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Posted in Debug, SystemVerilog, Test Suites, UVM |

 

Configuring Memory VIPs

Here, Synopsys Applications Consultant, Vaish Ramachandran, describes how best we can use Synopsys’ VIP Configuration Creator for configuring memory VIPs http://bit.ly/1JcvSII

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Posted in DDR, Debug, eMMC, HBM, LPDDR, Methodology, ONFi |