Verifying today’s complex designs is time consuming, as simulations run for long time and millions of transaction are executed. Traditional approach of debug is to dump all the information of millions of packets in a log file, however it would always be challenging to filter out specific transactions from the huge log file. For example, in case of AXI Protocol, a fixed number of outstanding transactions are allowed during simulation, it would always be difficult to find out such outstanding transaction in the huge log file of a single run of simulation or during interactive simulation. It is one of the biggest pain point of debugging.
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |
The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.
Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM |
Synopsys VC VIP provides Verdi Protocol Analyzer, a protocol and memory aware debug environment . In my previous blog Debugging Memory Protocols with the Verdi Protocol Analyzer, I discussed the value add for using the Verdi Protocol Analyzer to debug memory protocols easily and efficiently. Also, I described how easy it is to look at a specific command as a transaction rather than as interpreted signals. In this blog I’m going to show another feature that makes Verdi Protocol Analyzer the tool of choice for debugging memory protocol issues and for validating proper system behavior. Furthermore, the tool can be used for verification of the command sequencer and the interaction between the DUT and the memory models. The feature, we are going to look at today, is synchronizing transactions to the corresponding signals.
I ended my last blog post with a more-or-less complete NVMe VIP test-case example, trying to show everything from basic setup to doing an NVM Write followed by a Read. We are going to change gears a bit here, moving from the NVMe commands to some of the VIP features that are available to assist in your testing.
Debug continues to be one of the biggest hurdles faced by design and verification engineers. While designing a system that requires close interactions with memories, engineers often rely on print statements or waveform viewers to decipher signal behaviors over time, and/or their relationship relative to other signals over time. While this kind of ad-hoc debugging helps in understanding the behavior of a single signal, it does not work well when debugging protocols.
As sensors continue to get smaller, more powerful and cheaper, smartphones and other mobile devices incorporate over ten sensors to create self-aware devices. For instance, most recent models of Apple and Samsung handheld devices use several sensors to perform some of their coolest interface tricks: proximity sensor, accelerometer (motion sensor), ambient light sensor, moisture sensor, gyroscope, thermometer and magnetometer (compass). These sensors enable key capabilities for users including location services, health apps, fingerprint scanning and sophisticated gaming while optimizing power usage and WiFi access.
Companies developing complex ARM-based SoC designs have to constantly keep up with evolving interface standards and proliferating protocols a recurring problem that is resource-intensive and time-consuming. Orchestrating these multiple protocols is critical to extracting maximum SoC performance a key competitive differentiator. Achieving high performance while ensuring correct protocol behavior is best addressed by a combination of transaction-based, protocol-aware verification and debug environments. Synopsys VIP coupled with the Verdi unified debug platform spans verification planning, simulation debug, coverage, HW-SW debug and emulation debug, and helps tackle this challenge end-to-end.
Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging. This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure.