Verification Central

Archive for the 'Debug' Category

 

HBM3: Next generation memory standard for solving high density and complex computational problems

In this era of technology revolution, there is a continuous progression in domains like AI applications, high end servers, and graphics. These applications require fast processing and high densities for storing the data, where High Bandwidth Memory (HBM) provides the most viable memory technology solution. Our previous memory blog HBM2 memory for graphics, networking and HPC explored this protocol with data transfer rate of 2GT/s with stacked architecture of 8-Hi stacks (8 die).The HBM2-extension (HBM2E) architecture provided further improvement on top of HBM2 with 3.2 GT/s transfer rate and 12-Hi stack architecture with individual die density upto 8Gb and overall density of 24GB.

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Posted in Data Center, Debug, DesignWare, HBM, Uncategorized

 

Accelerate SoC Verification, Experts available

SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.

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Posted in ACE, AMBA, CXL, Debug, Display, Ethernet, HBM, Memory, Test Suites, Verification Service

 

Automating Testbench Creation to Accelerate Network-on-Chip Verification

Network-on-Chip (NoC) is a critical building block for many advanced and complex system-on-chips (SoCs). Having a complete verification solution to verify the functionality along with the performance (latency/bandwidth) is a must to ensure there are no functional bugs and no performance bottlenecks.

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Posted in Arm, Data Center, Debug, Mobile SoC, Uncategorized

 

Simplify Entertainment with HDMI 2.1 eARC

HDMI (High-Definition Multimedia Interface) has been a part of our entertainment systems for nearly two decades now. Though the look of the cable has remained the same over the years, the input has undergone many improvements since its release in 2002.

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Posted in Debug, Display, DisplayPort, Uncategorized, UVM

 

Optimizing HBM2E Runtime Performance

Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. When it comes to run time performance engineers not only develop the functionality but also can check performance of the design which is getting impacted from the new module. In traditional approach functionality development and performance analysis are sequential task and executed one after the other.

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Posted in Debug, HBM, UVM

 

HBM Performance Verification Made Easy

HBM2E (High Bandwidth Memory) is a high-performance 3D-stacked DRAM used in high-performance computing and graphic accelerators. It uses less power but posts higher bandwidth than graphics cards relying on DDR4 or GDDR5 memory. Validating the performance and utilization of memory is a big challenge for users due to complex structure of SoC and the subsystem attached to it such as memory subsystem, interconnect bus, and processor.

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Posted in Debug, Uncategorized

 

How to Reduce Memory Model Debug Time

Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?

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Posted in Debug, Memory, Uncategorized

 

Latest Buzz on Next Generation Protocols – USB4, PCIe 5.0, LPDDR5, and DDR5

We recently published the VIP Newsletter for Apr 2019, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in Data Center, DDR, Debug, LPDDR, Memory, Mobile SoC, PCIe, Processor Subsystems, Test Suites, Type C, USB

 

Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5

Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.

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Posted in Automotive, Data Center, DDR, Debug, DesignWare, DFI, HBM, LPDDR, Memory, Mobile SoC

 

Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols  and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized