VIP Central

Archive for the 'Debug' Category

 

Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols  and applications ranging from AI, Cloud, Display, Storage and […]

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Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized | Comments Off on Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

 

Trending Articles on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, and PCIe 5.0

We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance […]

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Posted in Automotive, Camera, CSI, Data Center, DDR, Debug, DFI, Display, DisplayPort, DSC, events, Flash, HDMI, LPDDR, Memory, MIPI, Mobile SoC, NVMe, PCIe, Storage, Test Suites, ToggleNAND, USB | Comments Off on Trending Articles on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, and PCIe 5.0

 

PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking

This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos. The […]

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Posted in Data Center, Debug, DesignWare, events, NVMe, PCIe, Storage | Comments Off on PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking

 

Accelerate Debug Productivity of Complex Serial Protocols

Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, which are insufficient for productive debugging. Debugging SoC and block level issues […]

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Posted in Automotive, Debug, Display, Mobile SoC, Type C, USB | Comments Off on Accelerate Debug Productivity of Complex Serial Protocols

 

MIPI M-PHY 4.1 – Preventing Data Loss in High Speed Mobility Devices

In today’s world of smartphones and tablets, high speed data at low power consumption is becoming increasingly important. MIPI M-PHY supports multiple applications with high data bandwidth and low power consumption which makes it a popular specification for mobile devices. Applications like JEDEC UFS 3.0 and MIPI UniPro 1.8 now support MIPI M-PHY 4.1 which […]

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Posted in Camera, Debug, Flash, Memory, MIPI, Mobile SoC, MPHY, UFS, Unipro | Comments Off on MIPI M-PHY 4.1 – Preventing Data Loss in High Speed Mobility Devices

 

Latest Buzz on Next Generation Protocols

We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.                     The Q1 2018 edition […]

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Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM | Comments Off on Latest Buzz on Next Generation Protocols

 

Next Generation Memory technologies: Ready to take the verification challenges?

Advancement in Memory technologies and the demand for faster and higher density configuration leaves verification engineers in a limbo. The Memory world is debating the next wave of memory protocols and technologies such as Next Generation DDR, HBM, and NVDIMM: DDR: Wishfully the next generation DDR specifications will bring many benefits to computers. With faster and […]

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Posted in Data Center, DDR, Debug, DFI, eMMC, events, Flash, HBM, HMC, LPDDR, Memory, ONFi, Storage, UFS | Comments Off on Next Generation Memory technologies: Ready to take the verification challenges?

 

Debug of AMBA AXI Outstanding Transactions

Verifying today’s complex designs is time consuming, as simulations run for long time and millions of transaction are executed. Traditional approach of debug is to dump all the information of millions of packets in a log file, however it would always be challenging to filter out specific transactions from the huge log file. For example, […]

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Posted in AMBA, Debug, Interconnects | Comments Off on Debug of AMBA AXI Outstanding Transactions

 

Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event. Synopsys hosted the annual “SoC Leaders Verify with Synopsys” Verification luncheon.  The luncheon featured industry experts and executives from Cavium, NXP, Qualcomm and Samsung, and drove our main messages of collaboration, with […]

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM | Comments Off on Verification Highlights from DAC 2016

 

Synopsys Verification Continuum at DAC 2016

The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers. Synopsys will feature its annual Verification Luncheon and Customer Panel that discusses the […]

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Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM | Comments Off on Synopsys Verification Continuum at DAC 2016