Verification Central

Archive for the 'PCIe' Category

 

Trending Articles on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, and PCIe 5.0

We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance analyzer and protocol debug. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in Automotive, Camera, CSI, Data Center, DDR, Debug, DFI, Display, DisplayPort, DSC, events, Flash, HDMI, LPDDR, Memory, MIPI, Mobile SoC, NVMe, PCIe, Storage, Test Suites, ToggleNAND, USB

 

PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking

This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos.

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Posted in Data Center, Debug, DesignWare, events, NVMe, PCIe, Storage

 

A Joint Webinar by Synopsys and NVM Express™ Organization – Virtualization and NVMe

With the rise of cloud computing and large scale data centers, both developers and consumers are demanding for more efficient ways to rapidly access their data. Seeing the advantage of its high performance, the storage industry is quickly adopting the Non-Volatile Memory Express (NVMe) standard. The NVMe™ standard continues to push the storage envelope with version 1.3 and beyond in all types of computing environments from mobile to data center. One of the key features of the NVMe™ standard is its ability to handle virtualization.

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Posted in Data Center, events, NVMe, PCIe, Storage, Uncategorized

 

Latest Buzz on Next Generation Protocols

We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM

 

PCIe PIPE 4.4.1: Enabler for PCIe Gen4

PCIe is a multi-layered serial bus protocol which implements dual-simplex link. It provides high speed data transfer and low latency owing to its dedicated point to point topology. To accelerate verification and device development time for PCIe based sub-systems, PIPE (PHY Interface for the PCI Express) architecture was defined by Intel. PIPE is a standard interface defined between PHY sub-layer (PCS – Physical Coding sub-layer) and MAC (Media Access Layer).

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Posted in Data Center, NVMe, PCIe, Storage

 

Jumping on the Demand for NVMe 1.3 Streams

Is your latest NVMe design taking advantage of Streams? Adoption of this new NVMe technology is gaining momentum with Synopsys customers. Streams are part of the new, optional, Directives feature introduced in the NVMe 1.3 specification. Directives allow the passing of metadata between hosts and controllers via existing NVMe commands. Streams are unique in that they are the only I/O based Directive available in the 1.3 specification.

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Posted in NVMe, PCIe, Storage

 

Is Your Design PCIe Gen5 Ready? Verify with Synopsys VIP and Testsuite

In June 2017, PCI-SIG announced the new PCI Express 5.0 specification, at the PCI-SIG DevCon. The new version of the specification doubled bit rate to 32GT/s per lane providing about 128GB/s bandwidth for a x16 Link (16 lanes). The chart below provides a comparison of bit-rate and bandwidth for the different PCIe Generations.

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Posted in Automotive, Data Center, DesignWare, PCIe

 

PCIe 4.0: A Quick Primer on New Features

‘Big Data’, ‘IoT’, ‘Mobile’, ‘Networking’ and ‘Storage’ applications are the key drivers for next generation high-performance systems. To meet the bandwidth requirement of the emerging applications, it was required to either increase the lane width or speed. Increasing the lane width isn’t cost effective and thus increasing speed is the best viable option. PCIe 4.0 has doubled the per lane throughput to 16GT/s, compared to 8GT/s for PCIe 3.0, delivering higher performance without increasing the lane width.

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Posted in NVMe, PCIe

 

PCI-SIG Conference – Did you Know?

The PCI-SIG Developers Conference 2017 took place in the Santa Clara, California convention center on June 7-8.  Today we will provide conference highlights, observations, and result of the 25-year anniversary dinner quiz.  The Synopsys team supporting the exhibition was kept very busy, running five live demos showing the latest in PCIe design and verification solutions. There was a lot of interest and queries from attendees regarding what’s new with PCIe VIP and TestSuite, and easy and effective debug using Verdi integrated protocol analyzer.

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Posted in events, PCIe

 

Latest Buzz in Verification IP

 

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Posted in ACE, AMBA, Automotive, CAN, CCI400, CHI, Data Center, Display, DisplayPort, eMMC, Ethernet AVB, FlexRay, HDCP, Interconnects, JESD, LIN, MIPI, PCIe, Processor Subsystems, UFS