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Archive for the 'PCIe' Category

 

PCIe Gen4 Test Suite with Spec Linking Demo

During the recent PCI-SIG Developers Conference 2016, held in Santa Clara, CA, there was a lot of interest from attendees regarding Synopsys PCIe Gen4 VIP and source code test suite.  One common question that was asked: How do we identify and maintain up to date tests that support the latest PCIe Gen4 specification? Demonstration: The […]

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Posted in Data Center, NVMe, PCIe, Processor Subsystems, Test Suites, Uncategorized | Comments Off on PCIe Gen4 Test Suite with Spec Linking Demo

 

PCI SIG Update: Latest on PCIe Gen4 0.7 VIP and Test Suite

The PCI-SIG Developers Conference 2016 was held at Santa Clara in last week and it was a great success. Our PCIe experts were there and we bring you the highlights of conference. There was a lot of interest and queries from attendees regarding our latest version of the PCI VIP for Gen 4.  The VIP supports […]

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Verification Highlights from DAC 2016

The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event. Synopsys hosted the annual “SoC Leaders Verify with Synopsys” Verification luncheon.  The luncheon featured industry experts and executives from Cavium, NXP, Qualcomm and Samsung, and drove our main messages of collaboration, with […]

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Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM | Comments Off on Verification Highlights from DAC 2016

 

Synopsys Verification Continuum at DAC 2016

The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers. Synopsys will feature its annual Verification Luncheon and Customer Panel that discusses the […]

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Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM | Comments Off on Synopsys Verification Continuum at DAC 2016

 

Full Utilization of 16 GT/s PCIe Gen 4 Bandwidth – 2

PCI express Gen 4 implementation is marching towards the Gen 4 0.7 release. It’s important that not only physical layer delivers the 16 GT/s rate, but also the entire protocol stack should be capable of saturating the full allocated bandwidth. To saturate the full bandwidth, following two key features are gaining traction: 10-bit extended tag […]

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Full Utilization of 16 GT/s PCIe Gen 4 Bandwidth

PCI Express Gen 4 has been under development since late 2011 and targeting impressive data rate of 16GT/s. Internet of things (IoT) continues to grow on its promise of everything connected, and it will be extremely important to deliver the promised 16 GT/s bandwidth for the next generation servers and communication equipment. PCI express Gen […]

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What’s Next in Storage – NVMe VIP?

Have you ever thought on the amount of data the world is producing every day? It runs in quintillions of bytes, and as we are writing this we have added to this ever growing rate of data production. With such an enormous rise in data production, cloud computing and large scale data center developers and […]

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Posted in Data Center, NVMe, PCIe, Storage | Comments Off on What’s Next in Storage – NVMe VIP?

 

NVMe VIP: Verification Features

I ended my last blog post with a more-or-less complete NVMe VIP test-case example, trying to show everything from basic setup to doing an NVM Write followed by a Read. We are going to change gears a bit here, moving from the NVMe commands to some of the VIP features that are available to assist […]

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Posted in Debug, NVMe, PCIe | Comments Off on NVMe VIP: Verification Features

 

Celebrating the Holiday Season with VIPs

The Holiday Season is upon us. As you stand in lines, wait for packages to arrive, keep in mind that Synopsys continues to provide you the highest level of service: support, available protocols and deployment of new titles that you, our current and future VIP customer, deserve. It has been a wonderful year — many […]

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Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB | Comments Off on Celebrating the Holiday Season with VIPs

 

PCIe Spread Spectrum Clocking (SSC) for Verification Engineers

Many of us who work primarily in digital verification and design are shielded from physical layer details. Only a handful of specialists closely follow these details. So for the rest of us, verifying and debugging Spread Spectrum Clocking (SSC) can be a daunting task. This blog post is a quick Q&A to give you a […]

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Posted in Methodology, PCIe | Comments Off on PCIe Spread Spectrum Clocking (SSC) for Verification Engineers