Verification Central

Archive for the 'PCIe' Category

 

Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum

Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling – gathering, storing, moving, processing, and dispersing – pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.

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Posted in CXL, Data Center, Interconnects, PCIe, Protocol Continuum

 

256Gb/s Ready Set Go : PCIe Gen6 Verification IP

Synopsys Industry’s First PCIe Gen6 VIP availability gives industry leaders a head start advantage for the verification of PCIe Gen6 based designs and meet time-to-market requirements with predictable quality. As PCIe Gen6 is the most significant and disruptive update to PCIe specification in the last decade, it is critically important and advantageous to start verification early and leverage Synopsys PCIe Gen6 VIP to deal with increased verification complexity as well as ensure backward compatibility with the prior generations through PCIe VIP Source Code Test Suite.

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Posted in Data Center, PCIe

 

Demystifying PCIe PIPE 5.1 SerDes Architecture

Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.

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Posted in PCIe, Uncategorized

 

Managing NVMe Verification Complexity

From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage.

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Posted in NVMe, PCIe, Storage

 

PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time

Billions of internet-connected devices and data-intensive real-time applications are expected to appear on the market in the near future and 100 Gigabit Ethernet (GE) speeds, common in data centers today, will just not be fast enough to handle the bandwidth. Therefore, we’re already anticipating the need for data center operators to migrate their networks from 100 GE to 400 GE, creating demand for faster memory and faster serial bus communications.

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Posted in PCIe

 

De-mystifying CXL: An overview

As Data Center and Artificial Intelligence applications take center stage , last few years have seen the advent of various high bandwidth interconnect technologies. Compute Express Link (CXL), is an aspiring new interconnect technology for high bandwidth devices such as accelerators with memory, high density compute cards, and GPU comprised accelerators. The specification is defined by CXL Consortium https://www.computeexpresslink.org/. Synopsys has developed a comprehensive ­­CXL verification subsystem, being already used by Early Adopters planning to release their first CXL applications. CXL verification subsystem leverages industry popular Synopsys PCI Express Verification IP. Synopsys recently introduced Industry’s first CXL IP solution. For more details refer Synopsys Delivers Industry’s First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs.

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Posted in CXL, DesignWare, Interconnects, Mobile SoC, PCIe

 

Signing off PCIe 5.0 Verification with Synopsys VIP

PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations.  Aligned with this, Synopsys also announced the collaboration of  its Design and Verification Solutions with  Astera Labs to Develop Industry’s First PCIe 5.0 Retimer SoC. Emerging applications like AI, cloud, data center, and 5G have been driving the exponential increase in bandwidth requirements and PCIe has evolved to meet these increasing requirements.

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Posted in CCIX, Data Center, PCIe, Uncategorized

 

Latest Buzz on Next Generation Protocols – USB4, PCIe 5.0, LPDDR5, and DDR5

We recently published the VIP Newsletter for Apr 2019, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in Data Center, DDR, Debug, LPDDR, Memory, Mobile SoC, PCIe, Processor Subsystems, Test Suites, Type C, USB

 

Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols  and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.

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Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized

 

PIPE 5.1.1 for PCIe 5.0, DP 1.4, USB 3.2, SATA, and Future Protocols

Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs, requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in latest PCIe, USB, DP, and SATA protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.

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Posted in Data Center, PCIe