Synopsys Industry’s First PCIe Gen6 VIP availability gives industry leaders a head start advantage for the verification of PCIe Gen6 based designs and meet time-to-market requirements with predictable quality. As PCIe Gen6 is the most significant and disruptive update to PCIe specification in the last decade, it is critically important and advantageous to start verification early and leverage Synopsys PCIe Gen6 VIP to deal with increased verification complexity as well as ensure backward compatibility with the prior generations through PCIe VIP Source Code Test Suite.
Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.
From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage.
Billions of internet-connected devices and data-intensive real-time applications are expected to appear on the market in the near future and 100 Gigabit Ethernet (GE) speeds, common in data centers today, will just not be fast enough to handle the bandwidth. Therefore, we’re already anticipating the need for data center operators to migrate their networks from 100 GE to 400 GE, creating demand for faster memory and faster serial bus communications.
Posted in PCIe
As Data Center and Artificial Intelligence applications take center stage , last few years have seen the advent of various high bandwidth interconnect technologies. Compute Express Link (CXL), is an aspiring new interconnect technology for high bandwidth devices such as accelerators with memory, high density compute cards, and GPU comprised accelerators. The specification is defined by CXL Consortium https://www.computeexpresslink.org/. Synopsys has developed a comprehensive CXL verification subsystem, being already used by Early Adopters planning to release their first CXL applications. CXL verification subsystem leverages industry popular Synopsys PCI Express Verification IP. Synopsys recently introduced Industry’s first CXL IP solution. For more details refer Synopsys Delivers Industry’s First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs.
PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations. Aligned with this, Synopsys also announced the collaboration of its Design and Verification Solutions with Astera Labs to Develop Industry’s First PCIe 5.0 Retimer SoC. Emerging applications like AI, cloud, data center, and 5G have been driving the exponential increase in bandwidth requirements and PCIe has evolved to meet these increasing requirements.
We recently published the VIP Newsletter for Apr 2019, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols and applications ranging from AI, Cloud, Display, Storage and Networking. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized
Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs, requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in latest PCIe, USB, DP, and SATA protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.
Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to use the well-established PCIe infrastructure to carry coherency packets across the link with little modification. CCIX specification is compatible with PCIe base specification 4.0. PCIe implementation is extended to implement a CCIX transaction layer, responsible for carrying the coherency messages.