The PCI-SIG Developers Conference 2017 took place in the Santa Clara, California convention center on June 7-8. Today we will provide conference highlights, observations, and result of the 25-year anniversary dinner quiz. The Synopsys team supporting the exhibition was kept very busy, running five live demos showing the latest in PCIe design and verification solutions. There was a lot of interest and queries from attendees regarding what’s new with PCIe VIP and TestSuite, and easy and effective debug using Verdi integrated protocol analyzer.
During the recent PCI-SIG Developers Conference 2016, held in Santa Clara, CA, there was a lot of interest from attendees regarding Synopsys PCIe Gen4 VIP and source code test suite. One common question that was asked: How do we identify and maintain up to date tests that support the latest PCIe Gen4 specification?
The PCI-SIG Developers Conference 2016 was held at Santa Clara in last week and it was a great success. Our PCIe experts were there and we bring you the highlights of conference.
Posted in PCIe |
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM |
The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.
Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM |
PCI express Gen 4 implementation is marching towards the Gen 4 0.7 release. It’s important that not only physical layer delivers the 16 GT/s rate, but also the entire protocol stack should be capable of saturating the full allocated bandwidth. To saturate the full bandwidth, following two key features are gaining traction:
Posted in PCIe |
PCI Express Gen 4 has been under development since late 2011 and targeting impressive data rate of 16GT/s. Internet of things (IoT) continues to grow on its promise of everything connected, and it will be extremely important to deliver the promised 16 GT/s bandwidth for the next generation servers and communication equipment.
Posted in PCIe |
We are living in a connected world and there are over a billion Ethernet devices around the world today. It is very interesting how Ethernet has evolved from a simple standard supporting 10 Mbps to multitude of speed modes and ubiquitous applications. From being a standard that traditionally evolved with 10x speed jumps (10M, 100M, 1G, 10G, 100G), it is now growing rapidly at non-10x speed modes (2.5G, 25G, 40G, 50G, 200G, and latest 400G) and covering diverse application areas to satisfy consumer needs.