New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency. Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.” Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.
SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM |
PCIe is a multi-layered serial bus protocol which implements dual-simplex link. It provides high speed data transfer and low latency owing to its dedicated point to point topology. To accelerate verification and device development time for PCIe based sub-systems, PIPE (PHY Interface for the PCI Express) architecture was defined by Intel. PIPE is a standard interface defined between PHY sub-layer (PCS – Physical Coding sub-layer) and MAC (Media Access Layer).
Is your latest NVMe design taking advantage of Streams? Adoption of this new NVMe technology is gaining momentum with Synopsys customers. Streams are part of the new, optional, Directives feature introduced in the NVMe 1.3 specification. Directives allow the passing of metadata between hosts and controllers via existing NVMe commands. Streams are unique in that they are the only I/O based Directive available in the 1.3 specification.
In June 2017, PCI-SIG announced the new PCI Express 5.0 specification, at the PCI-SIG DevCon. The new version of the specification doubled bit rate to 32GT/s per lane providing about 128GB/s bandwidth for a x16 Link (16 lanes). The chart below provides a comparison of bit-rate and bandwidth for the different PCIe Generations.
Arm TechCon 2017 took place at Santa Clara on 24-26th Oct, 2017. This year, Synopsys’ Arm® AMBA® protocol experts were on hand to demonstrate our verification automation solutions for Arm AMBA Coherent Interconnects. Synopsys Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances. Our experts also introduced our AMBA AutoPerformance solution to generate AMBA(CHI/ACE/AXI) interconnect performance verification stimulus. The AutoPerformance solution, based on Arm traffic profile specification, enables user to define traffic profiles for measurement of performance metrics like throughput, latency etc., and the stimulus is driven by VIP for AMBA (CHI/ACE/AXI).
First USB 3.2 VIP and TestSuite: Enhances the Verification Solution for USB IP, SoC and Type-C Subsystems
USB has literally become universal and present in every device ranging from smart phones and personal computers, IoT and wearables, storage and networking, consumer electronics and gaming consoles, automotive and many other emerging verticals. The success of USB can be attributed to innovation with each new generation—the capability to transfer data as well as supply power for charging devices and ease-of-use with a variety of connectors and form factors.
‘Big Data’, ‘IoT’, ‘Mobile’, ‘Networking’ and ‘Storage’ applications are the key drivers for next generation high-performance systems. To meet the bandwidth requirement of the emerging applications, it was required to either increase the lane width or speed. Increasing the lane width isn’t cost effective and thus increasing speed is the best viable option. PCIe 4.0 has doubled the per lane throughput to 16GT/s, compared to 8GT/s for PCIe 3.0, delivering higher performance without increasing the lane width.
DRAM memories are the ‘heart’ of any computational device, e.g. smart phones, laptops, servers etc. LPDDR4 was mainly designed to increase memory speed and efficiency for mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. It supports speeds up to 4267Mbps (double the speed of LPDDR3) and 1.1 V input/output buffer power, along with many other improvements compared to its predecessor (LPDDR3/LPDDR2). Below is a comparison of key features between all the three generations of LPDDR.