VIP Central

Archive for the 'HBM' Category

 

Increase Productivity with Synopsys Memory VIP

In this video, you will learn how to increase productivity with Synopsys Memory VIP.

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Posted in DDR, Debug, DFI, eMMC, Flash, HBM, HMC, LPDDR, Memory, Methodology, ONFi, UFS, UVM

 

Hands-on Memory Verification IP Workshops

Synopsys Memory Verification IP is modeled natively in SystemVerilog and supports the common verification standard UVM. Our models support 100% of the memory standard as specified by JEDEC.

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Posted in DDR, eMMC, HBM, LPDDR, Memory, Methodology, ONFi, UFS

 

Configuring Memory VIPs

Here, Synopsys Applications Consultant, Vaish Ramachandran, describes how best we can use Synopsys’ VIP Configuration Creator for configuring memory VIPs http://bit.ly/1JcvSII

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Posted in DDR, Debug, eMMC, HBM, LPDDR, Methodology, ONFi

 

Memory VIP Challenges

Behavioral Memory Models have been used for verification purposes for several years now. In the early days, modeling technology didn’t add much value to the usage model as designs were simple.

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Posted in DDR, eMMC, HBM, LPDDR, Memory, ONFi