SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.
In today’s digital age, networking requirements have become increasingly crucial. The possibility of unauthorized access to networks and confidential information have increased the need for secure network access.
Posted in Ethernet
IP traffic has been growing at a rate many could not have imagined. Driven by expanding Internet users and devices that yield faster wireless and fixed broadband access, the expeditious ethernet data rate has now reached to 400G. From 1Gbps in 1997, to 10Gbps in 2004, 100 Gbps in 2010, it took a while for the next set up to 400 Gbps.
Ethernet Time-Sensitive Network (TSN): A Boon for Automotive Audio-Video Bridging (AVB) Applications
Autonomous cars, vehicle communication and infotainment electronic systems are prevalent in today’s automobiles and everyday life. But, what does this mean for SoCs today?
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM
The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.
Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM
We are living in a connected world and there are over a billion Ethernet devices around the world today. It is very interesting how Ethernet has evolved from a simple standard supporting 10 Mbps to multitude of speed modes and ubiquitous applications. From being a standard that traditionally evolved with 10x speed jumps (10M, 100M, 1G, 10G, 100G), it is now growing rapidly at non-10x speed modes (2.5G, 25G, 40G, 50G, 200G, and latest 400G) and covering diverse application areas to satisfy consumer needs.
Posted in AMBA, Automotive, C-PHY, CAN, CSI, D-PHY, Data Center, DDR, DesignWare, DFI, Display, DSI, eMMC, Ethernet, Ethernet AVB, Flash, HBM, HDCP, HDMI, HMC, I3C, LPDDR, Memory, Methodology, MIPI, MPHY, NVMe, ONFi, PCIe, SATA, Storage, SystemVerilog, Test Suites, UFS, Unipro, USB
On Monday, Synopsys announced the availability of the industry’s first verification IP (VIP) and source code test suite to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard (400GbE). To understand how it will enable next generation networking and communication systems, we take a look at the evolution of the Ethernet.
Here, Synopsys R&D Director, Bernie DeLay, talks to EDACafe on the value of native SystemVerilog and UVM support in our VIP titles. He describes how our memory and protocol VIP have been built debug-friendly with Protocol Analyzer, and support constraint random verification for full functional coverage with back-annotation to executable verification plans.