VIP Central

Archive for the 'Data Center' Category

 

Accelerate SoC Verification, Experts available

SoC designs are growing more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world. Becoming an expert on each of the interconnect protocols is not going to shorten the verification schedules, reduce design productivity and expose design bugs that might only be found when used by the end consumer.

Continue Reading...

Posted in ACE, AMBA, CXL, Debug, Display, Ethernet, HBM, Memory, Test Suites, Verification Service

 

Synopsys at DVCon US 2021 – Join us!

Join us March 1- 4 at DVCon US 2021, to learn how we help customers optimize chips for power, performance, and cost and cut months off their project schedules.

Continue Reading...

Posted in Cloud, Data Center, DVCON

 

Securing Network Traffic using MACSec Over Ethernet

In today’s digital age, networking requirements have become increasingly crucial. The possibility of unauthorized access to networks and confidential information have increased the need for secure network access.

Continue Reading...

Posted in Ethernet

 

Automating Testbench Creation to Accelerate Network-on-Chip Verification

Network-on-Chip (NoC) is a critical building block for many advanced and complex system-on-chips (SoCs). Having a complete verification solution to verify the functionality along with the performance (latency/bandwidth) is a must to ensure there are no functional bugs and no performance bottlenecks.

Continue Reading...

Posted in Arm, Data Center, Debug, Mobile SoC, Uncategorized

 

256Gb/s Ready Set Go : PCIe Gen6 Verification IP

Synopsys Industry’s First PCIe Gen6 VIP availability gives industry leaders a head start advantage for the verification of PCIe Gen6 based designs and meet time-to-market requirements with predictable quality. As PCIe Gen6 is the most significant and disruptive update to PCIe specification in the last decade, it is critically important and advantageous to start verification early and leverage Synopsys PCIe Gen6 VIP to deal with increased verification complexity as well as ensure backward compatibility with the prior generations through PCIe VIP Source Code Test Suite.

Continue Reading...

Posted in Data Center, PCIe

 

Optimizing HBM2E Runtime Performance

Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. When it comes to run time performance engineers not only develop the functionality but also can check performance of the design which is getting impacted from the new module. In traditional approach functionality development and performance analysis are sequential task and executed one after the other.

Continue Reading...

Posted in Debug, HBM, UVM

 

Run Faster, Welcome 800G and Terabit Speeds with Ethernet 802.3ck

IP traffic has been growing at a rate many could not have imagined. Driven by expanding Internet users and devices that yield faster wireless and fixed broadband access, the expeditious ethernet data rate has now reached to 400G. From 1Gbps in 1997, to 10Gbps in 2004, 100 Gbps in 2010, it took a while for the next set up to 400 Gbps.

Continue Reading...

Posted in Ethernet, FlexE, Uncategorized

 

Demystifying PCIe PIPE 5.1 SerDes Architecture

Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.

Continue Reading...

Posted in PCIe, Uncategorized

 

Managing NVMe Verification Complexity

From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage.

Continue Reading...

Posted in NVMe, PCIe, Storage

 

PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time

Billions of internet-connected devices and data-intensive real-time applications are expected to appear on the market in the near future and 100 Gigabit Ethernet (GE) speeds, common in data centers today, will just not be fast enough to handle the bandwidth. Therefore, we’re already anticipating the need for data center operators to migrate their networks from 100 GE to 400 GE, creating demand for faster memory and faster serial bus communications.

Continue Reading...

Posted in PCIe