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Archive for the 'Data Center' Category

 

Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

We recently published the VIP Newsletter for Q4 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on PCIe 5.0, Arm® AMBA® 5 ACE5 and AXI5, CCIX and next generation MIPI and display protocols  and applications ranging from AI, Cloud, Display, Storage and […]

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Posted in ACE, AMBA, Audio, Automotive, AXI, Camera, CCIX, CHI, Data Center, Debug, DesignWare, Display, events, HDCP, HDMI, Interconnects, Interface Subsystems, MIPI, Mobile SoC, MPHY, PCIe, Processor Subsystems, Soundwire, Storage, Test Suites, Uncategorized | Comments Off on Latest In-depth Technical Articles and Videos on PCIe 5.0, AMBA 5, and CCIX

 

PIPE 5.1.1 for PCIe 5.0, DP 1.4, USB 3.2, SATA, and Future Protocols

Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs, requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in latest PCIe, USB, DP, and SATA protocol specifications, as […]

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Posted in Data Center, PCIe | Comments Off on PIPE 5.1.1 for PCIe 5.0, DP 1.4, USB 3.2, SATA, and Future Protocols

 

CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs

Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to […]

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Posted in CCIX, CHI, Data Center, Interconnects, PCIe, Storage | Comments Off on CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs

 

Trending Articles on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, and PCIe 5.0

We recently published the VIP Newsletter for Q3 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. The newsletter covers content on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, PCIe 5.0, next generation gaming displays, MIPI CSI-2 v2.1 for Automotive and IoT, and Verdi performance […]

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Posted in Automotive, Camera, CSI, Data Center, DDR, Debug, DFI, Display, DisplayPort, DSC, events, Flash, HDMI, LPDDR, Memory, MIPI, Mobile SoC, NVMe, PCIe, Storage, Test Suites, ToggleNAND, USB | Comments Off on Trending Articles on DFI 5.0 for DDR5/LPDDR5, NVMe 1.3, USB 3.2, and PCIe 5.0

 

PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking

This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos. The […]

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Posted in Data Center, Debug, DesignWare, events, NVMe, PCIe, Storage | Comments Off on PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking

 

How DFI 5.0 Ensures Higher Performance in DDR5/LPDDR5 Systems?

The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has […]

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Posted in Automotive, Data Center, DDR, DFI, LPDDR, Memory, Storage | Comments Off on How DFI 5.0 Ensures Higher Performance in DDR5/LPDDR5 Systems?

 

A Joint Webinar by Synopsys and NVM Express™ Organization – Virtualization and NVMe

With the rise of cloud computing and large scale data centers, both developers and consumers are demanding for more efficient ways to rapidly access their data. Seeing the advantage of its high performance, the storage industry is quickly adopting the Non-Volatile Memory Express (NVMe) standard. The NVMe™ standard continues to push the storage envelope with […]

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Posted in Data Center, events, NVMe, PCIe, Storage, Uncategorized | Comments Off on A Joint Webinar by Synopsys and NVM Express™ Organization – Virtualization and NVMe

 

LPDDR5: Enhancements in Bandwidth, Reliability, and Power for IoT, AI, and Image Processing

New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency.  Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar […]

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Posted in Automotive, Camera, DDR, DFI, Display, HBM, HMC, LPDDR, Memory, Mobile SoC | Comments Off on LPDDR5: Enhancements in Bandwidth, Reliability, and Power for IoT, AI, and Image Processing

 

Bye Bye Bottlenecks – Automated SoC Performance Verification is Here!

SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power […]

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Posted in Automotive, Data Center, DDR, DFI, events, HBM, LPDDR, Memory, Uncategorized | Comments Off on Bye Bye Bottlenecks – Automated SoC Performance Verification is Here!

 

Latest Buzz on Next Generation Protocols

We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.                     The Q1 2018 edition […]

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Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM | Comments Off on Latest Buzz on Next Generation Protocols