Is your SoC ready for HBM2E – 2x more capacity at 50% more speed
Highlights
Synopsys 10BaseT1-S VIP for your Automotive SoCs
10BASE-T1S specification is targeted for Automotive industry, developed with an objective to achieve collision free, deterministic transmission on a multi-drop network. Automotive applications require deterministic low-latency communication and do not need high data rates. 10BaseT1S protocol is used for sensor and actuator signaling. It allows the integration of diverse sensors into an automotive-Ethernet system and opens the door for new opportunities in Ethernet communication. The 10Base-T1S is a part of IEEE 802.3cg standard that supports data rates up to 10 Mbps over a single twisted pair for networks up to 25 meters.
Posted in Automotive, Ethernet, Ethernet AVB
Synopsys Introduces the Industry’s First Verification IP for Arm AMBA 5 CHI-F
Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 CHI protocol – CHI Issue F (CHI-F). AMBA 5 CHI-F is built on top of the existing AMBA CHI Issue E (CHI-E) specification (read our blog on AMBA CHI-E here), and introduces several exciting features related to the latest Arm architecture and optimized transaction flows.
Posted in AMBA, Arm, CHI, Data Center, Interconnects, Protocol Continuum, Test Suites
Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
Introduction:
Posted in Data Center, PCIe, Protocol Continuum, Test Suites
Synopsys Introduces Industry’s First CXL 3.0 Verification Solution
CXL 3.0 Introduction Compute Express Link™ (CXL™) 3.0 is an open standard that defines high-speed cache-coherent interconnect and memory expander interconnect for CPU-to-device and CPU-to-memory connections. It is built on PCI Express® (PCIe®) 6.0 r1.0 specifications and leverages PCIe for physical and electrical interface. Artificial Intelligence (AI) and Machine Learning (ML) applications and widespread smart devices (e.g., autonomous vehicles) are driving factors behind exponentially rising requirements to build high-performing data center units that involve CPUs connected with accelerator processors, memory attached devices, and SmartNICs. These systems demand low latency requirements for CPU-attached devices to perform compute-intensive operations on massive data while maintaining coherency. To meet the increasing performance and scale requirements of these systems, the CXL Consortium has evolved its standard through the introduction of CXL 3.0. CXL 3.0 Specification Highlights
Posted in AI, CXL, Data Center, DesignWare, Protocol Continuum, Verification Service
Synopsys Protocol Verification Solution for UCIe 1.0
Need for Multi-die Chiplets Interconnect
Posted in 5G, AI, Automotive, CXL, Data Center, Verification Service
Say Goodbye to blank screens with HDMI’s Quick Media Switching
Posted in AI, Data Center, Display, HDMI, Uncategorized
PCI Express Surges Forward: High Bandwidth Interconnect with PCIe 6.0
PCI-SIG® recently released the latest revision of the PCI Express® specification PCIe® 6.0. With 64GT/s raw data rate physical layer enabling up to 256 GB/s data transfers via 16-lane configuration. With this announcement PCIe continues to meet the industry’s need for high-bandwidth and low latency interconnect, whose potential could be leveraged by dependent storage (NVMe), and coherency (CXL) protocols.
Posted in Data Center, PCIe
HBM3: Next generation memory standard for solving high density and complex computational problems
In this era of technology revolution, there is a continuous progression in domains like AI applications, high end servers, and graphics. These applications require fast processing and high densities for storing the data, where High Bandwidth Memory (HBM) provides the most viable memory technology solution. Our previous memory blog HBM2 memory for graphics, networking and HPC explored this protocol with data transfer rate of 2GT/s with stacked architecture of 8-Hi stacks (8 die).The HBM2-extension (HBM2E) architecture provided further improvement on top of HBM2 with 3.2 GT/s transfer rate and 12-Hi stack architecture with individual die density upto 8Gb and overall density of 24GB.
Posted in Data Center, Debug, DesignWare, HBM, Uncategorized
Building Secure Chips with Verified CXL IDEs
Welcome to the wonderful and cryptic world of secured traffic with CXL being the latest specification to adopt it. As attacks on high-performance data centers become more sophisticated, the security standards must continuously adapt to better protect sensitive data and communications and ultimately protect our connected world. To this end, the CXL standards organization added the security requirement of Integrity and Data Encryption (IDE) to the CXL 2.0 specification.
Posted in 5G, CXL, Data Center, DesignWare
