Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, which are insufficient for productive debugging. Debugging SoC and block level issues using log files is tedious and time consuming. Design problems that appear in the later phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk.
High speed memory interface is a critical component to support high speed data in applications like personal computers, mobile phones, and digital cameras. These applications require a high capacity and high performance NAND flash memory, and Toggle2NAND is one of the most suitable NAND interfaces.
With the arrival of HDMI 2.1 comes an array of remarkable features including the capability to support up to 10K resolutions at 120Hz. Such high resolutions are supported for a wider range of display applications such as externally connected displays (i.e. PC monitors and televisions), embedded display interfaces within mobile systems, and automotive infotainment systems. But with higher resolutions comes the requirement for higher bandwidth.
Higher performance at lower power is the most critical requirement of SoC designs, specifically those targeted towards mobile and consumer electronics applications. VESA (Video Electronics Standards Association), the technical standards organization for computer display standards, came up with a new power saving feature called PSR (Panel Self Refresh) in eDP 1.3. It is also available as an optional feature in DisplayPort. PSR helps to extend battery life in mobile phones, notebooks, and tablets, and is quickly being adopted in high-end designs.
Flash storage is one of the most important component of a smart phone, and with every new version comes higher memory capacity and performance. The most rapidly adopted flash memory technology in recent years is Universal Flash Storage (UFS), with UFS v2.1 providing a maximum data rate of ~11Gbps. JEDEC has come up with the faster next-generation UFS v3.0 which uses MIPI UniPro v1.8 (Unified Protocol) and MIPI M-PHY v4.1 as interconnect layer.
In mid-2014, the USB Type-C standard was announced, which provided a thinner, reversible connector and ever evolving ecosystem of new platforms like MHL, DisplayPort, HDMI, and Thunderbolt over Type-C. USB Type-C is quickly being integrated into most high end and newly-released mid-range smart phones offering the reversible Type-C connector. It is also becoming the connector of choice for IoT, display, gaming, and other emerging applications. Synopsys’ Subsystem Verification Solution for USB Type-C™ is rapidly being adopted by customers. Read more about the adoption of Synopsys’ USB Type-C Subsystem Verification Solution by ASIX.
One could argue that camera has been the most fascinating feature of smart phones in recent years. The latest camera phones are capable of not only capturing minute details with multi-mega pixels, but also sensing the presence of various objects. MIPI CSI-2 (Camera Serial Interface) is a high-bandwidth interface between a camera and a host processor. MIPI CSI-2 v1.1 got introduced in 2011 to fulfill the basic camera requirements of mobile applications. Next generation MIPI CSI-2 v2.0 and v2.1 have evolved to meet the requirements of emerging imaging and vision applications like wearables, IoT, drones, automotive, and security surveillance beyond smart phones. Read our previous blog to know more about MIPI CSI-2 v2.0: Emerging Applications in IoT, Drones and Automotive. The new features of MIPI CSI-2 v2.1 are outlined below:
New applications like Cloud Computing, Artificial Intelligence, Autonomous cars, Augmented reality, Embedded vision are driving stricter requirements around memory performance and power efficiency. Memory is central to these systems, that require high bandwidth and speed along with lower power and lower cost. With these emerging market needs, the memory industry started to move from planar (2D) DRAMs to wide I/O or a 3D technology TSVs (Through Silicon Vertical interconnect access) such as HBM (high bandwidth memory). For more insight on HBM, read our blog “Next Generation Memory Technology for Graphics, Networking and HPC.” Low Power DRAM technology, evolved to the fifth-generation(LPDDR5) to deliver significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this blog, we discuss LPDDR5 new features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years.
SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?
We recently published the VIP Newsletter for Jan 2018, containing trending topics, leading solutions, in depth technical articles, videos, webinars, and updates on next generation protocols. In case you missed the latest buzz on Verification IP, you can read it here.
Posted in ACE, AMBA, Automotive, AXI, C-PHY, Camera, CHI, CSI, D-PHY, Data Center, DDR, Debug, Flash, Interconnects, LPDDR, Memory, Methodology, MIPI, Mobile SoC, NVMe, PCIe, Processor Subsystems, SPI, Storage, SystemVerilog, Test Suites, Type C, Uncategorized, UVM |