Verification Central

Archive for the 'Arm' Category

 

Get up to Speed with the Latest Arm AMBA AXI5 Features

The Arm® AMBA® 5 AXI protocol specification supports high-performance, high-frequency system designs for communication between manager and subordinate components. AMBA AXI5 protocols extend prior specification generations and add several important performance and scalability features which closely align these protocols to Arm AMBA CHI. Let’s look at some of the features of the AXI5 protocol in detail.

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Posted in AMBA, Arm, AXI

 

Synopsys Introduces the Industry’s First Verification IP for Arm AMBA 5 CHI-F

Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 CHI protocol – CHI Issue F (CHI-F). AMBA 5 CHI-F is built on top of the existing AMBA CHI Issue E (CHI-E) specification (read our blog on AMBA CHI-E here), and introduces several exciting features related to the latest Arm architecture and optimized transaction flows.

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Posted in AMBA, Arm, CHI, Data Center, Interconnects, Protocol Continuum, Test Suites

 

Cache Coherent Verification – New Features in AMBA®CHI

Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.

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Posted in AMBA, Arm

 

Automating Testbench Creation to Accelerate Network-on-Chip Verification

Network-on-Chip (NoC) is a critical building block for many advanced and complex system-on-chips (SoCs). Having a complete verification solution to verify the functionality along with the performance (latency/bandwidth) is a must to ensure there are no functional bugs and no performance bottlenecks.

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Posted in Arm, Data Center, Debug, Mobile SoC, Uncategorized