The Power Of HDMI ARC
HDMI ARC, What is it and Why You Should Care?
Posted in Display, HDMI, Uncategorized |
VIP Experts
Posts by VIP Experts:
Optimizing HBM2E Runtime Performance
Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. When it comes to run time performance engineers not only develop the functionality but also can check performance of the design which is getting impacted from the new module. In traditional approach functionality development and performance analysis are sequential task and executed one after the other.
Run Faster, Welcome 800G and Terabit Speeds with Ethernet 802.3ck
IP traffic has been growing at a rate many could not have imagined. Driven by expanding Internet users and devices that yield faster wireless and fixed broadband access, the expeditious ethernet data rate has now reached to 400G. From 1Gbps in 1997, to 10Gbps in 2004, 100 Gbps in 2010, it took a while for the next set up to 400 Gbps.
Posted in Ethernet, Uncategorized |
Faster closure, simulation acceleration to emulation
It’s a longstanding cliché, but it is true that verification is a marathon. An integrated verification platform accompanied by a systematic verification methodology are the building blocks to manage the verification complexity of modern system-on-chip (SoC) designs. High performance simulation environment is the foundation however it is not enough to reach to the verification closure that requires regressing hardware in conjunction to real application scenarios and software.
Posted in Audio, Automotive, Camera, IoT, Mobile SoC, UFS, UVM |
Demystifying PCIe PIPE 5.1 SerDes Architecture
Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.
Posted in PCIe, Uncategorized |
Managing NVMe Verification Complexity
From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage.
Industry’s First Verification IP for Arm AMBA5 CHI-D Enables Early Adopter Success
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time
Billions of internet-connected devices and data-intensive real-time applications are expected to appear on the market in the near future and 100 Gigabit Ethernet (GE) speeds, common in data centers today, will just not be fast enough to handle the bandwidth. Therefore, we’re already anticipating the need for data center operators to migrate their networks from 100 GE to 400 GE, creating demand for faster memory and faster serial bus communications.
Posted in PCIe |
Arm TechCon 2019 – Recap
Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.
Posted in AMBA, Interconnects, Mobile SoC, Processor Subsystems, Uncategorized |
Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings
We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.
Posted in LPDDR, Memory, Uncategorized |
Optimizing HBM2E Runtime Performance
Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. When it comes to run time performance engineers not only develop the functionality but also can check performance of the design which is getting impacted from the new module. In traditional approach functionality development and performance analysis are sequential task and executed one after the other.
Run Faster, Welcome 800G and Terabit Speeds with Ethernet 802.3ck
IP traffic has been growing at a rate many could not have imagined. Driven by expanding Internet users and devices that yield faster wireless and fixed broadband access, the expeditious ethernet data rate has now reached to 400G. From 1Gbps in 1997, to 10Gbps in 2004, 100 Gbps in 2010, it took a while for the next set up to 400 Gbps.
Posted in Ethernet, Uncategorized |
Faster closure, simulation acceleration to emulation
It’s a longstanding cliché, but it is true that verification is a marathon. An integrated verification platform accompanied by a systematic verification methodology are the building blocks to manage the verification complexity of modern system-on-chip (SoC) designs. High performance simulation environment is the foundation however it is not enough to reach to the verification closure that requires regressing hardware in conjunction to real application scenarios and software.
Posted in Audio, Automotive, Camera, IoT, Mobile SoC, UFS, UVM |
Demystifying PCIe PIPE 5.1 SerDes Architecture
Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.
Posted in PCIe, Uncategorized |
Managing NVMe Verification Complexity
From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage.
Industry’s First Verification IP for Arm AMBA5 CHI-D Enables Early Adopter Success
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time
Billions of internet-connected devices and data-intensive real-time applications are expected to appear on the market in the near future and 100 Gigabit Ethernet (GE) speeds, common in data centers today, will just not be fast enough to handle the bandwidth. Therefore, we’re already anticipating the need for data center operators to migrate their networks from 100 GE to 400 GE, creating demand for faster memory and faster serial bus communications.
Posted in PCIe |
Arm TechCon 2019 – Recap
Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer.
Posted in AMBA, Interconnects, Mobile SoC, Processor Subsystems, Uncategorized |
Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings
We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.
Posted in LPDDR, Memory, Uncategorized |
