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Mohit Bhardwaj

Posts by Mohit Bhardwaj:


Keeping Up with UCIe 1.1 Verification Using Synopsys VIP for UCIe

Ever since UCIe™ (Universal Chiplet Interconnect Express™) consortium was formed and version 1.0 of the UCIe specification was released, the chiplet/die-to-die ecosystem has been frenzied. IP architects and developers have their task cut-out for them – to come up with a robust design and implementation that benefits from the heterogenous system without compromising their power, performance, and area (PPA) goals. System architects and designers are busy putting the technology in their next generation SoCs. Verification teams are running against time to create test and coverage plans based on the integrated logic before they receive disintegrated chip RTL.

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Posted in 5G, CXL, Data Center, Interface Subsystems, PCIe


Ethernet Time-Sensitive Network (TSN): Synopsys Verification Solution for Complex TSN Specifications

The automotive industry has a critical requirement for accurate timing and guaranteed data delivery to ensure passenger safety and a seamless customer experience. Autonomous vehicles utilize advanced SoC architectures in the automotive ecosystem to address mission critical processing and timing requirements, increasing the importance of Time Sensitive Networking (TSN) features in automotive ethernet.

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Posted in Automotive, Ethernet, Ethernet AVB


NAND Flash Memory – Key Element For Your Multi-Die System Verification – Part-1

Introduction to NAND Flash Memory 

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Posted in Flash, Memory, Storage


Is your SoC ready for HBM2E – 2x more capacity at 50% more speed


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Posted in HBM, Memory


Synopsys Introduces the Industry’s First Verification IPs for Arm AMBA 5 AXI-J and APB-E

Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 AXI and APB – AXI Issue J (AXI-J) and APB issue E (APB-E). These new specifications introduce several exciting features related to the latest Arm architecture and optimized transaction flows.

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Posted in AMBA, Arm, AXI


Using Synopsys Smart Monitors to Improve System Performance of Your Arm SoCs


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Posted in AXI, Uncategorized, ZeBu EP1


Synopsys TileLink Interconnect Verification IP for RISC-V SoCs

What is RISC-V?

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Posted in Interface Subsystems, Processor Subsystems, Uncategorized


Addressing the Verification Challenges of Panel Self Refresh in eDP

What is eDP (Embedded Display Port)?

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Posted in Display, DisplayPort


Achieve Functional Safety for Automotive and Digital Ecosystems using MIPI CSE

Today, the automotive industry is experiencing an advanced evolution which demands need for an ever-increasing bit-depths, frame rates, camera and display resolutions, and most significantly functional safety. To address these challenges and to support future architectures, the MIPI Alliance developed MIPI Automotive SerDes Solutions (MASS)  which is an end-to-end framework for connecting sensors, cameras, displays and many other industry standardized protocols with functional safety and security. In this blog we will review the features and nuances of MIPI CSE™ (Camera Service Extension) one of the key components in the MASS connectivity framework, and explain how Synopsys Verification IP (VIP) for MIPI solutions provide a comprehensive set of methodology, verification and productivity features to support these protocols.

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Posted in Automotive, Camera, CSI, IoT, MIPI


Reviewing the Latest Arm AMBA ACE5-Lite Protocol Specification Updates

In this blog we will review the newest features released as part of the Arm® AMBA® ACE5-Lite protocol, said to improve throughput and meet the low power demands of ever evolving complex multicore SoCs including cache coherency.

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Posted in ACE, AMBA, Arm, CHI