If you are a Synopsys Verdi user, what simulator are you using? The answer could have a significant impact on your verification productivity. For example, if you use a non-Synopsys simulator, you may experience longer than normal regression runs when signals are dumped, and in some scenarios the time to load the Fast Signal Database (FSDB) into Verdi increases too. In this blog we’ll share the native integrations that the Synopsys Verdi® debug solution and Synopsys VCS® functional verification solution share that will improve your designs performance and debug productivity. Let’s explore these Verdi and VCS optimizations a bit more.
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Recently we wrote about how AI-driven debug automation technology can accelerate the root-cause analysis of regression failures. In that blog we introduced the Synopsys Verdi Regression Debug Automation (RDA) technology that helped customers like MediaTek achieve a 4X improvement in identifying root-causes of failures in their design. This blog will take a deeper look into the components of this RDA technology, explain how they work and how users can take advantage to achieve similar results.
Leveraging a Unified Emulation and Prototyping System to Address Verification Requirements Across the Chip Development Cycle
Author: Tom De Schutter, VP Marketing and System Solutions, Synopsys Systems Design Group
Posted in ZeBu EP1
PCI-SIG® recently released the latest revision of the PCI Express® specification PCIe® 6.0. With 64GT/s raw data rate physical layer enabling up to 256 GB/s data transfers via 16-lane configuration. With this announcement PCIe continues to meet the industry’s need for high-bandwidth and low latency interconnect, whose potential could be leveraged by dependent storage (NVMe), and coherency (CXL) protocols.