Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
What is RISC-V?
Reduced Instruction Set Computer Architecture (RISC) is an instruction set architecture (ISA) which implies a basic bridge between hardware and software. RISC enables the communication between an assembly language programmer and a processor by defining a set of simple instructions that are combined to perform various complex instructions.
Both RISC and Complex Instruction Set Computer (CISC) approaches try to optimize a CPU’s processing time. In RISC, cycles required per instruction are reduced while instructions per program are increased. But in CISC, the number of instructions per program are reduced while cycles per instruction are increased.
Execution time = # of instructions per program X # of cycles per instruction
As a result, RISC is more of a software-based ISA as the software must take care of sending necessary simple instructions to execute an application. While CISC is a hardware-based ISA as instruction in CISC is complex and therefore needs complex instruction decoding.
RISC-V is an open standard instruction set architecture based on established RISC principles. Unlike most other ISA designs, RISC-V is provided under open-source licensing, which allows for broad use across the industry.
Understanding the role of TileLink in RISC-V Architecture
The developers of RISC-V developed a parametrizable SoC generator called RocketChip which uses the TileLink specification as an interconnect for its multiprocessors, accelerators, and DMA engines, etc.
TileLink is an open-source chip scale interconnect standard providing coherent memory-mapped access to memory and other devices. It is also a fast and scalable interconnect which provides both low latency and high throughput transfers.
Key Benefits of TileLink:
- TileLink is designed to support cache coherent shared memory
- Cache coherence is a concern in a multi-core (multiple processors on a single chip) environment where each processor has a separate cache memory. In this case it is possible to have different copies of shared data – i.e., One copy in the main memory and one in each cache memory – and when one of the copies of data is changed then the other copies are left with invalid data without the notification of the change. Cache coherence is the concept used to make sure changes in the values of shared data are updated through the system. TileLink supports MESI equivalent protocol to tackle cache coherent issues.
- TileLink provides deadlock-freedom for any conforming SoC
- TileLink supports any topology that can be defined as a Directed Acyclic Graph (DAG), where agents are the vertices and links are the edges, with edges directed from driver interfaces to receiver interfaces. By supporting DAG, TileLink is free of any loops or cycles in its topology.
- TileLink is equipped with out-of-order completion to improve throughput for concurrent operations.
- TileLink offers stateless bus width adaptation.
How does the TileLink Network Works?
An example of a basic TileLink network is shown in the figure below. An agent containing a driver interface is connected to another agent containing a receiver interface over a Link. The driver agent sends a request to a receiver agent, the receiver agent will respond to the original requestor confirming that sent data or permissions are received.
Within every link, Tilelink defines five channels that are logically independent of each other over which messages can be exchanged by agents. The TileLink specification defines priority amongst the channel messages in the order of “A << B << C << D << E”, increasing priority which must be strictly enforced to make sure messages within the TileLink network never enters a routing or hold-and-wait loop thereby avoiding deadlock.
Messages in TileLink are composed of beats, each beat contains the following:
- Unchanging message header
- Unchanging Opcode (the message type)
- Unchanging size (the base-2 logarithm of the number of bytes in the data payload)
- An optional multi-beat data payload
Beats are regulated by channel specific independent “ready” & “valid” signals. The sender and receiver need to provide valid and ready signals respectively to enable bit transfer. Once the request message has been initiated its corresponding response message may be sent at any of the following times:
- After a pre-defined delay
- On the same cycle as the first beat of the request has been accepted
- Before all the beats of request message have been accepted
TileLink forbids timeouts within the TileLink network, guaranteeing that a TileLink network will never deadlock. TileLink protocol defines rules known as forward processing rules that govern the conditions under which a receiving agent may reject a beat of a message by changing the ready signal.
Synopsys VIP for TileLink
Synopsys® Verification IP for TileLink provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure.
Features of Synopsys TileLink VIP Include:
- Supports TileLink 1.8.0 and 1.8.1 specifications
- Driver, receiver, and crossbar agents
- TL-UL, TL-UH, and TL-C conformance levels
- All channels
- All request and response messages
- Comprehensive same-channel and cross-channel delays
- Data widths: 32, 64, 128, 256, 512, 1024-bits
- All burst-size up to 4KB
- Out-of-order responses
- User-defined FIFO mode (in-order) responses
An example of a basic architecture where Synopsys Verification IP for TileLink can be used in a multi-level cache memory application is shown in the figure below. Each component (core, cache L1, cache L2, main memory) connected to the TileLink interconnect through the TileLink driver or receiver interface can be integrated with its corresponding driver or receiver Verification IP agent.
As shown, when multiple cores with separate cache memory are sharing the main memory or a higher-level cache, the TileLink crossbar agent can be used to maintain the cache coherence between them.
Summary
Even though RISC-V is not the very first attempt at free and open-source processor IP, it has been the first to intrigue the industry on such a large scale. This has given TileLink specification flexibility and an open approach, generating huge innovation and growth potential.
Synopsys VIP for TileLink can be integrated, configured, and customized with minimal effort.
Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® and Synopsys HAPS® systems.
You can read a previous TileLink blog here for even more information.
