Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
If you have not already deployed best practices of using Verification Plans, Functional and Timing Coverage Models in your Memory projects, learn why it is recommended…
Key Attributes of Functional and Timing Coverage Closure Flow
• Automated coverage report generation with the flexibility to specify the types different types of coverage to be enabled
• Automatic back annotation of coverage data into test plan, identifying progress against coverage goals
• Rapid identification of remaining coverage points linked to unencrypted source code, enabling faster coverage closure
• Users can extend the built-in coverage to add their own bins based on built-in VIP sampling events and groups or create their own groups with any sampling event or data
• Simulator based coverage utilities like the exclusion of bins/coverpoints/covergroups can be leveraged for the scenarios/settings not supported by IP/Subsystem
Synopsys Memory Models (VIP) have built-in verification plans, functional and timing coverage models to accelerate coverage closure. The coverage models are provided to help run complete verification scenarios across multiple combinations of configuration settings, mode register settings, features, and timing parameters.
Synopsys Memory VIP supports the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI (DDR5, LPDDR5, DFI 5.0, HBM3, GDDR6, and NVDIMM-P/N) and native integrations and optimizations with VCS and Verdi.
Coverage model implementation is based on System Verilog constructs (covergroups, coverpoints, bins, illegal bins) and it is “Protocol Specification Version aware” which means coverpoints/bins are ignored if not applicable to the configured protocol specification version.
Synopsys Memory VIP coverage models comprise of,
• Verification Plan – The verification plan shows how each functional coverage group is directly mapped to the protocol specification scenario. Verification plan is hierarchical with sub-plans based on the different types of coverage.
• Functional Coverage Model – The functional coverage support includes coverage for Configuration, Mode Registers, Checks, Commands, State, Trainings, Timing Parameters, Toggle, along with the valid cross coverages.
• Timing Coverage Model – The timing coverage support includes coverage for Command to Command delays, Power down time, Self-Refresh time, Setup/Hold, along with the cross coverage with different data rates and all the valid mode register configurations (burst length, data width, latencies etc.)
The unique, flexible coverage architecture of Synopsys Memory VIP makes it possible to be easily plugged into any Verilog/SV/UVM/VMM based testbench setup. For more information visit, https://www.synopsys.com/verification/verification-ip/memory.html
Synopsys supports over 100+ Industry Leading Verification IP and source code Test Suites for protocols such as Arm® AMBA®, DRAM Memory (GDDR6, DDR5, LPDDR5), Flash Memory, Ethernet (800G), MIPI, CXL, PCIe (6.0), SAS, SATA, USB (4.0/3.x, Type-C). For a complete list of Verification IP and Test Suites, visit www.synopsys.com/vip.
As an industry leader for complete Protocol Verification solutions, Synopsys is committed to providing you with the resources you need to accelerate your designs.