10BASE-T1S specification is targeted for Automotive industry, developed with an objective to achieve collision free, deterministic transmission on a multi-drop network. Automotive applications require deterministic low-latency communication and do not need high data rates. 10BaseT1S protocol is used for sensor and actuator signaling. It allows the integration of diverse sensors into an automotive-Ethernet system and opens the door for new opportunities in Ethernet communication. The 10Base-T1S is a part of IEEE 802.3cg standard that supports data rates up to 10 Mbps over a single twisted pair for networks up to 25 meters.
Recently we wrote about how AI-driven debug automation technology can accelerate the root-cause analysis of regression failures. In that blog we introduced the Synopsys Verdi Regression Debug Automation (RDA) technology that helped customers like MediaTek achieve a 4X improvement in identifying root-causes of failures in their design. This blog will take a deeper look into the components of this RDA technology, explain how they work and how users can take advantage to achieve similar results.
The Arm® AMBA® 5 AXI protocol specification supports high-performance, high-frequency system designs for communication between manager and subordinate components. AMBA AXI5 protocols extend prior specification generations and add several important performance and scalability features which closely align these protocols to Arm AMBA CHI. Let’s look at some of the features of the AXI5 protocol in detail.
Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 CHI protocol – CHI Issue F (CHI-F). AMBA 5 CHI-F is built on top of the existing AMBA CHI Issue E (CHI-E) specification (read our blog on AMBA CHI-E here), and introduces several exciting features related to the latest Arm architecture and optimized transaction flows.
In a 5G world, fast and secure connectivity is important. The JEDEC Universal Flash Storage (UFS) version 4.0 helps to ensure this is possible in our everyday devices. As an added security element, a Replay Protected Memory Block (RPMB) is included in UFS devices as a means to store encrypted data securely, only accessible by authentication.
Leveraging a Unified Emulation and Prototyping System to Address Verification Requirements Across the Chip Development Cycle
Author: Tom De Schutter, VP Marketing and System Solutions, Synopsys Systems Design Group
Posted in ZeBu EP1
Verification of today’s devices takes an enormous amount of computing power. Advanced methodologies require a huge number of automated tests to exercise all parts of the design. Regression tests must run frequently to ensure that changes do not break previously verified functionality. Most projects cannot afford to buy enough compute resources and simulation licenses to meet their peak demand, and many projects struggle to build their own verification infrastructure. A more flexible approach is required.
Posted in Cloud
Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
CXL 3.0 Introduction Compute Express Link™ (CXL™) 3.0 is an open standard that defines high-speed cache-coherent interconnect and memory expander interconnect for CPU-to-device and CPU-to-memory connections. It is built on PCI Express® (PCIe®) 6.0 r1.0 specifications and leverages PCIe for physical and electrical interface. Artificial Intelligence (AI) and Machine Learning (ML) applications and widespread smart devices (e.g., autonomous vehicles) are driving factors behind exponentially rising requirements to build high-performing data center units that involve CPUs connected with accelerator processors, memory attached devices, and SmartNICs. These systems demand low latency requirements for CPU-attached devices to perform compute-intensive operations on massive data while maintaining coherency. To meet the increasing performance and scale requirements of these systems, the CXL Consortium has evolved its standard through the introduction of CXL 3.0. CXL 3.0 Specification Highlights
Need for Multi-die Chiplets Interconnect